公开(公告)号：US11080095B2

公开(公告)日：2021-08-03

申请号：US15870766

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10599481B2

公开(公告)日：2020-03-24

申请号：US15870770

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Constantin Pistol ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  Russell A. Blaine ,  Kushal Dalmia

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20190155656A1

公开(公告)日：2019-05-23

申请号：US16195429

申请日：2018-11-19

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  James M. Magee

IPC: G06F9/50 ,  G06F9/48

Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.

公开(公告)号：US10140157B2

公开(公告)日：2018-11-27

申请号：US14290791

申请日：2014-05-29

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  James M. Magee

IPC: G06F9/50 ,  G06F9/48

Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.

公开(公告)号：US09772959B2

公开(公告)日：2017-09-26

申请号：US14292123

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Kushal Dalmia ,  Joseph Sokol, Jr. ,  Andrew W. Vogan ,  Matthew J. Byom

IPC: G06F13/18 ,  G06F3/06 ,  G06F13/38 ,  G06F9/00

CPC classification number: G06F13/18 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/00 ,  G06F13/385

Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.

公开(公告)号：US09400677B2

公开(公告)日：2016-07-26

申请号：US13893631

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Benjamin C. Trumbull ,  Adam C. Swift ,  Russell A. Blaine ,  Benjamin H. Nham ,  Kari E. Christianson

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/466 ,  G06F9/526 ,  G06F2209/522 ,  G06F2209/523

Abstract: An operating system of a data processing system receives a request from a first process to acquire an exclusive lock for accessing a resource of the data processing system. A second priority of a second process is increased to reduce total execution time. The second process is currently in possession of the exclusive lock for performing a transactional operation with the resource. The second priority was lower than a first priority of the first process. The operating system notifies the second process to indicate that another process is waiting for the exclusive lock to allow the second process to complete or roll back the transactional operation and to release the exclusive lock thereafter.

Abstract translation: 数据处理系统的操作系统从第一进程接收到获取用于访问数据处理系统的资源的排他锁的请求。 增加第二个进程的第二个优先级，以减少总执行时间。 第二个进程当前拥有执行与该资源的事务操作的排他锁。 第二个优先次序低于第一个进程的第一优先事项。 操作系统通知第二进程以指示另一进程正在等待排他锁以允许第二进程完成或回滚事务操作并且此后释放排他锁。

公开(公告)号：US20150347262A1

公开(公告)日：2015-12-03

申请号：US14292466

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Amit K. Vyas ,  Albert S. Liu ,  Anand Ramadurai ,  Drew A. Schmitt ,  Russell A. Blaine ,  Karen Crippes

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/50

CPC classification number: G06F11/3409 ,  G06F9/5011 ,  G06F9/5022 ,  G06F9/505 ,  G06F11/3003 ,  G06F11/3013 ,  G06F11/302 ,  G06F11/3024 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2209/5022

Abstract: A method and apparatus of a device for performance management by terminating application programs that consume an excessive amount of system resources is described. The device receives a resource consumption threshold and a detection period. The device further monitors a resource usage of an application program. The device determines whether the resource usage of the application program exceeds the resource consumption threshold for the detection period. The device further terminates the application program when the resource usage exceeds the resource consumption threshold for the detection period.

Abstract translation: 描述了通过终止消耗过多的系统资源的应用程序来执行性能管理的设备的方法和装置。 设备接收资源消耗阈值和检测周期。 该设备进一步监视应用程序的资源使用情况。 该设备确定应用程序的资源使用是否超过检测周期的资源消耗阈值。 当资源使用超过检测周期的资源消耗阈值时，设备进一步终止应用程序。

公开(公告)号：US10956220B2

公开(公告)日：2021-03-23

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F1/3206 ,  G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10884811B2

公开(公告)日：2021-01-05

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200379810A1

公开(公告)日：2020-12-03

申请号：US16808021

申请日：2020-03-03

Applicant: Apple Inc.

Inventor： Kushal Dalmia ,  Andrey V. Talnikov ,  Lionel D. Desai ,  Russell A. Blaine

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34

Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.