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    Apparatus and method for suspending execution of a thread in response to a hint instruction
    21.
    发明授权
    Apparatus and method for suspending execution of a thread in response to a hint instruction 有权

    公开(公告)号：US09977679B2

    公开(公告)日：2018-05-22

    申请号：US14935820

    申请日：2015-11-09

    Applicant: ARM Limited

    Inventor： Ian Michael Caulfield ,  Antony John Penton ,  Robert Gwilym Dimond

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3867 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3009 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3861

    Abstract: An apparatus and method are provided for processing instructions from a plurality of threads. The apparatus comprises a processing pipeline to process instructions, including fetch circuitry to fetch instructions from a plurality of threads for processing by the processing pipeline, and execution circuitry to execute the fetched instructions. Execution hint instruction handling circuitry is then responsive to the fetch circuitry fetching an execution hint instruction for a first thread, to treat the execution hint instruction, at least in a presence of a suspension condition, as a predicted branch instruction with a predicted behavior, and to cause the fetch circuitry to suspend fetching of instructions for the first thread. The execution circuitry is then arranged to execute the predicted branch instruction with a behavior different to the predicted behavior, in order to trigger a misprediction condition. The fetch circuitry is then responsive to the misprediction condition to resume fetching of instructions for the first thread. This provides a reliable mechanism for temporarily suspending fetching of instructions for a thread in response to a hint instruction, whilst still reliably resuming fetching in due course.

    Method and apparatus for interrupt handling
    22.
    发明授权
    Method and apparatus for interrupt handling 有权
    中断处理方法和装置

    公开(公告)号：US09330035B2

    公开(公告)日：2016-05-03

    申请号：US13900777

    申请日：2013-05-23

    Applicant: ARM LIMITED

    Inventor： Anthony Jebson ,  Richard Roy Grisenthwaite ,  Michael Alexander Kennedy ,  Ian Michael Caulfield

    IPC: G06F13/24 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/4818

    Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.

    Abstract translation: 数据处理装置包括多个系统寄存器和一组用于控制进入中断的处理的中断处理寄存器。 所述设备还包括被配置为执行所述多个执行级别的软件的处理电路，以及被配置为将所述输入中断路由到中断处理软件的中断控制器电路，所述中断处理软件被配置为在所述多个执行级中的一个执行级别运行，并且将访问控制电路 配置为根据所述多个执行级别中的一个来动态地控制对至少一些所述中断处理寄存器的访问，所述多个执行级别中的所述进入中断被路由到。 配置为在特定执行级别运行的中断处理软件无法访问中断处理寄存器，用于处理被配置为以更特权的执行级运行的中断处理软件的不同输入中断。

    APPARATUS AND METHOD FOR POINTER AUTHENTICATION
    24.
    发明申请
    APPARATUS AND METHOD FOR POINTER AUTHENTICATION 有权

    公开(公告)号：US20240386094A1

    公开(公告)日：2024-11-21

    申请号：US18577970

    申请日：2022-07-07

    Applicant: Arm Limited

    Inventor： Alexander Alfred Hornung ,  Ian Michael Caulfield

    IPC: G06F21/54 ,  G06F9/38 ,  G06F21/44

    Abstract: An apparatus has processing circuitry to execute instructions and address prediction storage circuitry to store address prediction information for use in predicting upcoming instructions to be executed by the processing circuitry. The processing circuitry is responsive to an instruction to generate a pointer signature for a pointer to generate the pointer signature for the pointer based on an address of the pointer and a cryptographic key. The address prediction storage circuitry is also configured to store address prediction information for the pointer, the address prediction information including the pointer. The processing circuitry is responsive to an instruction to authenticate a given pointer to obtain, based on the address prediction information for the given pointer, a predicted pointer signature; compare the predicted pointer signature with a pointer signature identified by the instruction to authenticate; and responsive to the comparing detecting a match, determine that the given pointer is valid.

    Register-based matrix multiplication with multiple matrices per register
    26.
    发明授权
    Register-based matrix multiplication with multiple matrices per register 有权

    公开(公告)号：US11288066B2

    公开(公告)日：2022-03-29

    申请号：US16626701

    申请日：2018-06-08

    Applicant: ARM LIMITED

    Inventor： David Hennah Mansell ,  Rune Holm ,  Ian Michael Caulfield ,  Jelena Milanovic

    IPC: G06F9/302 ,  G06F9/30 ,  G06F17/16

    Abstract: Techniques for performing matrix multiplication in a data processing apparatus are disclosed, comprising apparatuses, matrix multiply instructions, methods of operating the apparatuses, and virtual machine implementations. Registers, each register for storing at least four data elements, are referenced by a matrix multiply instruction and in response to the matrix multiply instruction a matrix multiply operation is carried out. First and second matrices of data elements are extracted from first and second source registers, and plural dot product operations, acting on respective rows of the first matrix and respective columns of the second matrix are performed to generate a square matrix of result data elements, which is applied to a destination register. A higher computation density for a given number of register operands is achieved with respect to vector-by-element techniques.

    Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
    28.
    发明授权
    Handling stalling event for multiple thread pipeline, and triggering action based on information access delay 有权

    公开(公告)号：US10552160B2

    公开(公告)日：2020-02-04

    申请号：US15987113

    申请日：2018-05-23

    Applicant: ARM Limited

    Inventor： Ian Michael Caulfield ,  Max John Batley ,  Chiloda Ashan Senarath Pathirane

    IPC: G06F9/38

    Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.

    Apparatus and method for controlling allocation of data into a cache storage
    29.
    发明授权
    Apparatus and method for controlling allocation of data into a cache storage 有权

    公开(公告)号：US10394716B1

    公开(公告)日：2019-08-27

    申请号：US15946848

    申请日：2018-04-06

    Applicant: Arm Limited

    Inventor： Frederic Claude Marie Piry ,  Peter Richard Greenhalgh ,  Ian Michael Caulfield ,  Albin Pierrick Tonnerre ,  Jeffrey Allen Kehl

    IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/0808 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: An apparatus and method are provided for controlling allocation of data into cache storage. The apparatus comprises processing circuitry for executing instructions, and a cache storage for storing data accessed when executing the instructions. Cache control circuitry is arranged, while a sensitive allocation condition is determined to exist, to be responsive to the processing circuitry speculatively executing a memory access instruction that identifies data to be allocated into the cache storage, to allocate the data into the cache storage and to set a conditional allocation flag in association with the data allocated into the cache storage. The cache control circuitry is then responsive to detecting an allocation resolution event, to determine based on the type of the allocation resolution event whether to clear the conditional allocation flag such that the data is thereafter treated as unconditionally allocated, or to cause invalidation of the data in the cache storage. Such an approach can reduce the vulnerability of a cache to speculation-based cache timing side-channel attacks.

    Arbitration of requests requiring a variable number of resources
    30.
    发明申请
    Arbitration of requests requiring a variable number of resources 审中-公开

    公开(公告)号：US20170185542A1

    公开(公告)日：2017-06-29

    申请号：US14757577

    申请日：2015-12-24

    Applicant: ARM LIMITED

    Inventor： Max John Batley ,  Ian Michael Caulfield ,  Chris Abernathy

    IPC: G06F13/16 ,  G06F12/12

    Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

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