公开(公告)号：US10095518B2

公开(公告)日：2018-10-09

申请号：US14941840

申请日：2015-11-16

Applicant: ARM LIMITED

Inventor： Andrew James Antony Lees ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh

IPC: G06F9/30

Abstract: Instruction queue circuitry maintains an instruction queue to store fetched instructions. Instruction decode circuitry decodes instructions dispatched from the queue. The instruction decode circuitry allocates processor resource(s) for use in execution of the decoded instruction. Detection circuitry detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry. Dispatch circuitry dispatches an instruction from the queue to the instruction decode circuitry and allows deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry.

公开(公告)号：US09213547B2

公开(公告)日：2015-12-15

申请号：US13826553

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Max John Batley

IPC: G06F9/30 ,  G06F9/00

CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。

公开(公告)号：US11263133B2

公开(公告)日：2022-03-01

申请号：US16979624

申请日：2019-03-12

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Stephan Diestelhorst ,  Nikos Nikoleris ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Albin Pierrick Tonnerre

IPC: G06F12/0802

Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

公开(公告)号：US10579389B2

公开(公告)日：2020-03-03

申请号：US14929904

申请日：2015-11-02

Applicant: ARM Limited

Inventor： Ian Michael Caulfield ,  Chiloda Ashan Senerath Pathirane

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group.

公开(公告)号：US10521368B2

公开(公告)日：2019-12-31

申请号：US14757577

申请日：2015-12-24

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Ian Michael Caulfield ,  Chris Abernathy

IPC: G06F13/16 ,  G06F12/128 ,  G06F12/12

Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

公开(公告)号：US10402203B2

公开(公告)日：2019-09-03

申请号：US15578477

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behavior to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).

公开(公告)号：US09952871B2

公开(公告)日：2018-04-24

申请号：US14731789

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Simon John Craske ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3889

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

公开(公告)号：US11803388B2

公开(公告)日：2023-10-31

申请号：US17266759

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Ian Michael Caulfield ,  Albin Pierrick Tonnerre

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3832 ,  G06F9/30098 ,  G06F9/3836

Abstract: An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.

公开(公告)号：US11526615B2

公开(公告)日：2022-12-13

申请号：US16976166

申请日：2019-03-12

Applicant: Arm Limited

Inventor： Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Ian Michael Caulfield ,  Albin Pierrick Tonnerre

IPC: G06F21/57 ,  G06F9/30 ,  G06F9/38 ,  G06F11/36 ,  G06F21/55 ,  G06F21/71

Abstract: An apparatus comprises processing circuitry 14 to perform data processing in response to instructions, the processing circuitry supporting speculative processing of read operations for reading data from a memory system 20, 22; and control circuitry 12, 14, 20 to identify whether a sequence of instructions to be processed by the processing circuitry includes a speculative side-channel hint instruction indicative of whether there is a risk of information leakage if at least one subsequent read operation is processed speculatively, and to determine whether to trigger a speculative side-channel mitigation measure depending on whether the instructions include the speculative side-channel hint instruction. This can help to reduce the performance impact of measures taken to protect against speculative side-channel attacks.

公开(公告)号：US11429393B2

公开(公告)日：2022-08-30

申请号：US14938285

申请日：2015-11-11

Applicant: ARM LIMITED

Inventor： Vladimir Vasekin ,  Ian Michael Caulfield ,  Chiloda Ashan Senarath Pathirane

IPC: G06F9/38

Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.