公开(公告)号：US10394716B1

公开(公告)日：2019-08-27

申请号：US15946848

申请日：2018-04-06

Applicant: Arm Limited

Inventor： Frederic Claude Marie Piry ,  Peter Richard Greenhalgh ,  Ian Michael Caulfield ,  Albin Pierrick Tonnerre ,  Jeffrey Allen Kehl

IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/0808 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: An apparatus and method are provided for controlling allocation of data into cache storage. The apparatus comprises processing circuitry for executing instructions, and a cache storage for storing data accessed when executing the instructions. Cache control circuitry is arranged, while a sensitive allocation condition is determined to exist, to be responsive to the processing circuitry speculatively executing a memory access instruction that identifies data to be allocated into the cache storage, to allocate the data into the cache storage and to set a conditional allocation flag in association with the data allocated into the cache storage. The cache control circuitry is then responsive to detecting an allocation resolution event, to determine based on the type of the allocation resolution event whether to clear the conditional allocation flag such that the data is thereafter treated as unconditionally allocated, or to cause invalidation of the data in the cache storage. Such an approach can reduce the vulnerability of a cache to speculation-based cache timing side-channel attacks.