公开(公告)号：US20180129269A1

公开(公告)日：2018-05-10

申请号：US15647063

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/32 ,  G06F9/44

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20180088660A1

公开(公告)日：2018-03-29

申请号：US15721200

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20170249164A1

公开(公告)日：2017-08-31

申请号：US15273413

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F12/1009 ,  G06F12/14 ,  G06F13/42

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20160224442A1

公开(公告)日：2016-08-04

申请号：US14870923

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F11/20 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F11/2028 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2201/805

Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.

Abstract translation: 用于在两个（或多个）可独立操作的处理器之间控制恢复错误信息的方法和装置。 本公开提供了在致命错误的情况下保留错误信息，在独立可操作的处理器之间协调复位条件并且实现用于在一系列潜在致命错误中进行错误信息恢复的一致框架的解决方案。 在一个示例性实施例中，应用处理器（AP）和基带处理器（BB）实现中止处理器和掉电处理程序序列，其能够在广泛的崩溃情况下进行错误恢复。 在一种变型中，AP和BB之间的信号断言使AP能够在错误恢复过程成功完成后重置BB。

公开(公告)号：US20160077989A1

公开(公告)日：2016-03-17

申请号：US14856283

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4282

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wirless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

Abstract translation: 用于经由物理总线接口进行数据汇聚和复用一个或多个虚拟总线接口的方法和装置。 各种公开的实施例被配置为：（i）通过单个物理接口复用多个逻辑接口，（ii）交换会话管理和逻辑接口控制，（iii）管理流量控制，（iv）提供关于数据的“提示” ，元数据），和/或（v）填充数据分组。 在一个特定实现中，所述方法和装置被配置为在无启用便携式电子设备（例如支持蜂窝的智能电话机）内使用，并利用高速串行物理总线接口的一个或多个特征。

公开(公告)号：US08989071B2

公开(公告)日：2015-03-24

申请号：US13755743

申请日：2013-01-31

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Ben-Heng Juang ,  Arjuna Sivasithambaresan

IPC: G08C17/00 ,  H04W52/02

CPC classification number: H04W52/0209 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/164

Abstract: A method includes inter-chip data communications between a power-managed integrated circuit (IC) and a peer IC. The peer IC generates a data frame and prepends a discardable preamble of a predefined size to a payload of the data frame. The predefined size is a size not less than a size of data discarded by the power-managed IC upon the power-managed IC receiving a data frame while in a low-power state. The peer IC transmits the data frame to the power-managed IC. The power-managed IC, while in a low-power state, may receive the data frame from the peer IC and in response to receiving the data frame, begin exiting the low-power state. The power-managed IC, while exiting the low-power state, may discard a portion of the data frame such as for example, some or all of the discardable preamble, without discarding payload.

Abstract translation: 一种方法包括功率管理集成电路（IC）和对等IC之间的片间数据通信。 对等IC产生数据帧，并将预定义大小的可丢弃前导码添加到数据帧的有效载荷。 在功率管理IC在低功率状态下接收数据帧时，预定义的尺寸是不小于由功率管理IC所丢弃的数据的大小的尺寸。 对等IC将数据帧发送到功率管理IC。 功率管理IC在处于低功率状态时可以从对等IC接收数据帧，并且响应于接收到数据帧，开始退出低功率状态。 功率管理IC在退出低功率状态时可以丢弃数据帧的一部分，例如可丢弃的前导码中的一些或全部，而不丢弃有效载荷。

公开(公告)号：US20130332764A1

公开(公告)日：2013-12-12

申请号：US13631360

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Ben-Heng Juang ,  Arun G. Mathias ,  Karan Sanghi ,  Arjuna Sivasithambaresan

IPC: G06F1/00

CPC classification number: G06F1/3278 ,  G06F13/42 ,  G06F2213/0038 ,  H04L49/109 ,  Y02D10/151 ,  Y02D10/157

Abstract: One embodiment of the present invention provides a system that facilitates intelligent inter-processor communication with power optimization. The system comprises a memory, a first router, a second router, a first physical link coupled between the first router and the second router, and a second physical link coupled between the first router and the second router. Furthermore, the system comprises a first communication bus implemented on the first physical link, as well as a second communication bus implemented on the second physical link. Note that the second communication bus provides lower power consumption and lower bandwidth than the first communication bus. During operation, the system receives a packet at the first router, wherein the packet is destined for the second router. Next, the system selects either the first communication bus or the second communication bus over which to route the packet. Finally, the system routes the packet according to the selection.

Abstract translation: 本发明的一个实施例提供一种通过功率优化促进智能处理器间通信的系统。 该系统包括存储器，第一路由器，第二路由器，耦合在第一路由器和第二路由器之间的第一物理链路，以及耦合在第一路由器和第二路由器之间的第二物理链路。 此外，该系统包括在第一物理链路上实现的第一通信总线以及在第二物理链路上实现的第二通信总线。 注意，第二通信总线提供比第一通信总线更低的功耗和更低的带宽。 在操作期间，系统在第一路由器处接收分组，其中分组指定给第二路由器。 接下来，系统选择要路由分组的第一通信总线或第二通信总线。 最后，系统根据选择路由数据包。

公开(公告)号：US11176068B2

公开(公告)日：2021-11-16

申请号：US16780743

申请日：2020-02-03

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/40 ,  G06F13/28

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

公开(公告)号：US11176064B2

公开(公告)日：2021-11-16

申请号：US16588557

申请日：2019-09-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav V. Petkov

IPC: G06F13/16 ,  G06F12/0831 ,  G06F15/167 ,  G06F15/173

Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

公开(公告)号：US20210026715A1

公开(公告)日：2021-01-28

申请号：US16691370

申请日：2019-11-21

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F13/362 ,  H04L25/00 ,  G06F9/46 ,  G06F13/16 ,  G06F13/42

Abstract: Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive RTP data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack. In this manner, the AP's scheduler can coordinate/accommodate digital audio tasks within the context of its other tasks (e.g., to enable intelligent sleep and wake-up operation, load balancing, memory usage, and/or any number of other processor management functions).