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28 条记录 (耗时 0.028 秒)

    Circuit for generating internal power voltage
    21.
    发明申请
    Circuit for generating internal power voltage 审中-公开
    产生内部电源电压的电路

    公开(公告)号：US20070024351A1

    公开(公告)日：2007-02-01

    申请号：US11321875

    申请日：2005-12-30

    申请人： Yong-Gu Kang

    发明人： Yong-Gu Kang

    IPC分类号： G05F1/10

    CPC分类号： G05F1/465

    摘要： There is provided a circuit for generating an internal power voltage capable of stably controlling an internal power voltage before generating a reference voltage during an initial power-up operation of a semiconductor device. The circuit for generating an internal power voltage includes: an internal power reset controller for outputting a control signal in response to an activated reference signal and an external power voltage wherein the reference signal is activated after the external power voltage is inputted; and an internal power generator for generating the internal power voltage using the external power voltage in response to the activated reference signal wherein the internal power generator is disabled in response to the control signal.

    摘要翻译： 提供了一种用于在半导体器件的初始上电操作期间产生能够稳定地控制内部电源电压的电路，该电路产生参考电压。 用于产生内部电源电压的电路包括：内部电源复位控制器，用于响应于激活的参考信号和外部电源电压输出控制信号，其中参考信号在输入外部电源电压之后被激活; 以及内部发电机，用于响应于激活的参考信号，利用外部电源电压产生内部电力电压，其中内部功率发生器响应于控制信号被禁用。

    Data output circuit of memory device
    22.
    发明授权
    Data output circuit of memory device 有权
    存储器件的数据输出电路

    公开(公告)号：US07081784B2

    公开(公告)日：2006-07-25

    申请号：US11008254

    申请日：2004-12-10

    申请人： Yong Gu Kang

    发明人： Yong Gu Kang

    IPC分类号： H03K3/00

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222

    摘要： A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command and outputting a plurality of output enable signals in response to a rising DLL clock and a falling DLL clock. The output driving unit drives data synchronously with respect to the rising DLL clock and the falling DLL clock in response to the output enable signals at a read mode. The output enable control unit disables the falling DLL clock when the output enable signals are all disabled. As a result, current consumption is reduced because the falling DLL clock is generated only when the output enable signal is generated.

    摘要翻译： 存储装置的数据输出电路包括输出使能信号发生单元，输出驱动单元，输出驱动单元和输出使能控制单元。 输出使能信号生成单元响应于读取命令产生参考输出使能信号，并且响应于升高的DLL时钟和下降的DLL时钟而输出多个输出使能信号。 响应于读取模式下的输出使能信号，输出驱动单元相对于上升的DLL时钟和下降的DLL时钟同步地驱动数据。 当输出使能信号全部被禁止时，输出使能控制单元禁止下降的DLL时钟。 结果，由于仅当产生输出使能信号时才产生下降的DLL时钟，所以消耗电流。

    Semiconductor device
    24.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08406074B2

    公开(公告)日：2013-03-26

    申请号：US12914164

    申请日：2010-10-28

    申请人： Yong-Gu Kang

    发明人： Yong-Gu Kang

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618

    摘要： A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command.

    摘要翻译： 半导体器件分别包括至少两个存储体的多个存储体组和与该多个存储体组一一对应的多个地址计数器。 响应于组组刷新命令执行所选择的组组的刷新操作。

    LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME
    25.
    发明申请
    LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME 有权
    水平更换电路和具有相同功能的半导体器件

    公开(公告)号：US20110204953A1

    公开(公告)日：2011-08-25

    申请号：US12756772

    申请日：2010-04-08

    申请人： Yong-Gu Kang ,  Choung-Ki Song

    发明人： Yong-Gu Kang ,  Choung-Ki Song

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113

    摘要： A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.

    摘要翻译： 电平移位器电路包括上拉单元，其配置为响应于以第一电压电平的幅度摆动的输入信号，将输出节点上拉至高于第一电压电平的第二电压电平;下拉单元 被配置为响应于输入信号来下拉输出节点，以及保护单元，连接在输出节点和下拉单元之间，以防止输出节点的电压被施加到下拉单元。

    TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS
    26.
    发明申请
    TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS 有权
    测试电路，使用其的半导体存储器件以及半导体存储器件的测试方法

    公开(公告)号：US20110128804A1

    公开(公告)日：2011-06-02

    申请号：US12650727

    申请日：2009-12-31

    申请人： Yong Gu KANG

    发明人： Yong Gu KANG

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5006

    摘要： A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

    摘要翻译： 半导体存储装置的测试电路包括：测试控制信号生成单元，被配置为在测试信号被使能之后启用有效信号，并且基本上将控制信号保持在使能状态直到预充电定时信号 已启用 以及预充电控制单元，其被配置为当初始位线预充电信号处于禁用状态时，将控制信号反转为输出反相信号作为位线预充电信号。

    Delay locked loop for controlling duty rate of clock
    28.
    发明授权
    Delay locked loop for controlling duty rate of clock 有权
    延迟锁定环，用于控制时钟的占空比

    公开(公告)号：US07372311B2

    公开(公告)日：2008-05-13

    申请号：US11319720

    申请日：2005-12-29

    申请人： Yong-Gu Kang

    发明人： Yong-Gu Kang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0805

    摘要： There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

    摘要翻译： 提供了能够通过熔丝选项或EMRS输入来控制时钟占空比的DLL。 DLL包括第一时钟缓冲器，第二时钟缓冲器，第一延迟线，第二延迟线，移位寄存器，第一占空比控制单元，第二占空比控制单元，第一DLL驱动器，第二DLL驱动器， 延迟模型，相位比较器和移位控制单元。 在DLL中，第一占空比控制单元和第二占空比控制单元分别通过EMRS输入或熔丝选项来控制第一和第二延迟线的输出时钟的每个占空比。 因此，可以通过EMRS输入或保险丝选项来控制DLL时钟的占空比。