公开(公告)号：US08882547B2

公开(公告)日：2014-11-11

申请号：US13543048

申请日：2012-07-06

申请人： Yoshiaki Asakuma ,  Takashi Kawamoto ,  Toshiyuki Takii

发明人： Yoshiaki Asakuma ,  Takashi Kawamoto ,  Toshiyuki Takii

IPC分类号： H01R4/36 ,  H01R4/42

CPC分类号： H01R4/42

摘要： A screw terminal block 10A includes a terminal plate 12 provided with an insertion hole 12a through which a terminal screw 11 is inserted; and a fastening plate 13 provided with a screw hole 13a to which the terminal screw 11 inserted through the insertion hole 12a is screwed. The screw hole 13a is formed in the fastening plate 13, and a protrusion 13b is provided at right and left sides of the fastening plate 13. Upper and lower locking pieces 12b protruding toward the fastening plate 13 are provided at right and left side ends of the terminal plate 12 to sandwich the protrusion 13b therebetween. The locking piece 12b of the terminal plate 12 and the protrusion 13b of the fastening plate 13 are engaged with each other to restrict the relative rotation of the fastening plate 13 and the terminal plate 12.

摘要翻译： 螺钉端子块10A包括端子板12，端子板12设置有插入孔12a，端子螺钉11通过插入孔12a插入; 以及设置有螺钉孔13a的紧固板13，通过插入孔12a插入的端子螺钉11被螺纹连接。 螺钉孔13a形成在紧固板13中，突起13b设置在紧固板13的左右侧。向固定板13突出的上下锁定片12b设置在紧固板13的右侧和左侧 端子板12将突起13b夹在其间。 端子板12的锁定片12b和紧固板13的突起13b彼此接合以限制紧固板13和端子板12的相对旋转。

公开(公告)号：US08289057B2

公开(公告)日：2012-10-16

申请号：US13351745

申请日：2012-01-17

申请人： Takashi Kawamoto

发明人： Takashi Kawamoto

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/0893 ,  H03L7/10 ,  H03L7/18

摘要： A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

摘要翻译： 即使半导体集成电路的制造过程具有波动，也具有期望的频率特性的锁相环（PLL）。 半导体集成电路包括PLL和控制单元。 PLL具有相位检波器，环路滤波器，压控振荡器（VCO）和分频器。 VCO包括电压 - 电流转换器（VIC）和环形振荡器。 响应于控制电压，VIC产生用于设置环形振荡器的每个工作电流的控制电流。 控制单元将PLL切换到其开环的校准工作周期及其闭环的正常工作周期。

公开(公告)号：US20120237295A1

公开(公告)日：2012-09-20

申请号：US13413931

申请日：2012-03-07

申请人： Takashi Kawamoto ,  Takafumi Matsuda ,  Masaaki Miyamoto ,  Hironori Sadakane ,  Katsunori Yokokawa ,  Minoru Tsukahara ,  Junichi Kawaura ,  Yuki Motoyama

发明人： Takashi Kawamoto ,  Takafumi Matsuda ,  Masaaki Miyamoto ,  Hironori Sadakane ,  Katsunori Yokokawa ,  Minoru Tsukahara ,  Junichi Kawaura ,  Yuki Motoyama

IPC分类号： E01C11/02

CPC分类号： E01D19/06

摘要： A jointing structure comprising multiple steps provided face to face at the coaxially built traveling path ends with an expansion gap between, multiple elastic members respectively mounted inside the multiple steps, and a joint block mounted on the multiple elastic members across the expansion gap. Multiple supporting blocks and one or more than one intermediate joint block are mounted inside the multiple steps with the joint block between. The multiple supporting blocks, the joint block and the one or more than one intermediate joint block are of concrete. The elastic members are joined together across the expansion gap. The elastic member on one side is fixed to the inside of the step on one side and then subjected to deformation toward the bridge girder axis, and thereafter, the elastic member on the other side is fixed to the inside of the step on the other side.

摘要翻译： 包括在同轴构造的行进路径上面对面设置的多个台阶的接合结构，分别安装在多个台阶内的多个弹性构件之间的膨胀间隙，以及安装在多个弹性构件上的膨胀间隙的接头块。 多个支撑块和一个或多于一个中间接合块安装在多个台阶内，其间具有接合块。 多个支撑块，接头块和一个或多个中间接头块是具体的。 弹性构件通过膨胀间隙连接在一起。 一侧的弹性部件固定在一侧的台阶的内侧，然后朝向桥梁轴线变形，此后，另一侧的弹性部件固定在台阶的另一侧的内侧 。

公开(公告)号：US20120112843A1

公开(公告)日：2012-05-10

申请号：US13351745

申请日：2012-01-17

申请人： Takashi KAWAMOTO

发明人： Takashi KAWAMOTO

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/0893 ,  H03L7/10 ,  H03L7/18

摘要： A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

摘要翻译： 即使半导体集成电路的制造过程具有波动，也具有期望的频率特性的锁相环（PLL）。 半导体集成电路包括PLL和控制单元。 PLL具有相位检波器，环路滤波器，压控振荡器（VCO）和分频器。 VCO包括电压 - 电流转换器（VIC）和环形振荡器。 响应于控制电压，VIC产生用于设置环形振荡器的每个工作电流的控制电流。 控制单元将PLL切换到其开环的校准工作周期及其闭环的正常工作周期。

公开(公告)号：US07957710B2

公开(公告)日：2011-06-07

申请号：US12216092

申请日：2008-06-30

申请人： Takashi Kawamoto ,  Takashi Oshima ,  Taizo Yamawaki ,  Manabu Nakamura

发明人： Takashi Kawamoto ,  Takashi Oshima ,  Taizo Yamawaki ,  Manabu Nakamura

IPC分类号： H04B1/04 ,  H04M1/00

CPC分类号： H03F1/0227 ,  H03F1/0205 ,  H03F1/32 ,  H03F3/24 ,  H03F2200/102 ,  H03F2200/99

摘要： A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

摘要翻译： DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件，分别处理N个分离信号; 以及加法器，其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带，并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如，配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离，并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。

公开(公告)号：US20110037505A1

公开(公告)日：2011-02-17

申请号：US12843926

申请日：2010-07-27

申请人： Takashi KAWAMOTO

发明人： Takashi KAWAMOTO

IPC分类号： H03L7/06

CPC分类号： H03L7/0807 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/193 ,  H03L7/1976 ,  H04L7/0004 ,  H04L7/0337

摘要： A semiconductor chip area is reduced and the possibility of malfunction in generation of reproduction data and a reproduction clock is reduced. A transceiver comprises a clock data recovery circuit, a deserializer, a serializer, a PLL circuit, and a frequency detector. The clock data recovery circuit extracts a reproduction clock and reproduction data in response to a receive signal and a clock signal generated by the PLL circuit. The deserializer generates parallel receive data from the reproduction clock and the reproduction data, and the serializer generates a serial transmit signal from parallel transmit data and the clock signal. The detector detects a difference in frequency of the receive signal and the clock signal, and generates a frequency control signal. In response to the frequency control signal, the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency.

摘要翻译： 半导体芯片面积减小，并且生成再现数据和再现时钟的故障的可能性降低。 收发器包括时钟数据恢复电路，解串器，串行器，PLL电路和频率检测器。 时钟数据恢复电路响应于由PLL电路产生的接收信号和时钟信号，提取再现时钟和再现数据。 解串器从再现时钟和再现数据产生​​并行接收数据，串行器从并行发送数据和时钟信号生成串行发送信号。 检测器检测接收信号和时钟信号的频率差，并产生频率控制信号。 响应于频率控制信号，PLL电路控制时钟信号的周期，以减少频率差。

公开(公告)号：US07859345B2

公开(公告)日：2010-12-28

申请号：US12337459

申请日：2008-12-17

申请人： Takashi Kawamoto

发明人： Takashi Kawamoto

IPC分类号： H03L7/093

CPC分类号： H03L7/0898 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976

摘要： The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

摘要翻译： 半导体集成电路包括PLL电路，其包括相位频率比较器1，第一和第二电荷泵2和3，环路滤波器4，电压控制振荡器5和分频器6. PLL电路的操作模式包括 停止锁定的待机状态，开始锁定的锁定响应操作以及继续通过锁定响应操作开始的锁定的稳定的锁定操作。 在稳定锁定操作中，进行设定使得第二电荷泵3的充电/放电电流比第一充电泵2小。第一和第二充电泵2和3响应于输出而对环路滤波器4进行充电和放电 相位相反的相位频率比较器1。 在锁定开始的锁定响应操作中，第二电荷泵3相位反向停止充电和放电。

公开(公告)号：US07446614B2

公开(公告)日：2008-11-04

申请号：US11403968

申请日：2006-04-14

申请人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

发明人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC分类号： H03L7/085 ,  H03L7/089 ,  H03L7/099

CPC分类号： H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

摘要： A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 将来自阈值可变逆变器的另一输出信号的直流分量输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US08334726B2

公开(公告)日：2012-12-18

申请号：US12953385

申请日：2010-11-23

申请人： Takashi Kawamoto

发明人： Takashi Kawamoto

IPC分类号： H03L7/093

CPC分类号： H03L7/0898 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976

摘要： The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

摘要翻译： 半导体集成电路包括PLL电路，其包括相位频率比较器1，第一和第二电荷泵2和3，环路滤波器4，电压控制振荡器5和分频器6. PLL电路的操作模式包括 停止锁定的待机状态，开始锁定的锁定响应操作以及继续通过锁定响应操作开始的锁定的稳定的锁定操作。 在稳定锁定操作中，进行设定使得第二电荷泵3的充电/放电电流比第一充电泵2小。第一和第二充电泵2和3响应于输出而对环路滤波器4进行充电和放电 相位相反的相位频率比较器1。 在锁定开始的锁定响应操作中，第二电荷泵3相位反向停止充电和放电。

公开(公告)号：US20120190225A1

公开(公告)日：2012-07-26

申请号：US13389349

申请日：2010-08-03

申请人： Keisuke Bessyo ,  Kouji Higashide ,  Takashi Kawamoto ,  Toshiyuki Takii

发明人： Keisuke Bessyo ,  Kouji Higashide ,  Takashi Kawamoto ,  Toshiyuki Takii

IPC分类号： H01R24/00 ,  H01R29/00

CPC分类号： H01R25/003 ,  H01R13/64 ,  H01R24/76 ,  H01R2103/00

摘要： A plug receptacle includes a housing having at least one outlet unit to which a plug is adapted to be connected to supply a DC power to the plug, and a cable, connected to the housing, for supplying the DC power to the housing. The outlet unit includes a plug-receiving portion having a plurality of substantially circular pin-inserting holes into which plug pins of the plug are inserted and an insertion groove formed to surround a periphery of the plug-receiving portion. The plug-receiving portion has a substantially quadrangular shape viewed from a front side thereof. The insertion groove is adapted to receive a surrounding wall of the plug and has a substantially quadrangular shape viewed from the front side. The pin-receiving holes are arranged along one side of the plug-receiving portion serving as a reference side and offset closer to the reference side than an opposite side to the reference side.

摘要翻译： 插头插座包括壳体，该壳体具有至少一个出口单元，插头适于连接到插头上以向插头提供直流电力，以及连接到壳体的电缆，用于将DC电力提供给壳体。 出口单元包括插头接收部分，该插头接收部分具有多个基本上圆形的插销孔，插头插头插入该插孔中，插入槽形成为围绕插头接收部分的周边。 插头接收部分具有从其前侧观察的大致四边形。 插入槽适于容纳插塞的周围壁，并且具有从前侧观察的大致四边形的形状。 销接收孔沿作为基准侧的插头接收部分的一侧布置，并且比与参考侧相反的一侧偏离比参考侧。