公开(公告)号：US08239638B2

公开(公告)日：2012-08-07

申请号：US11758303

申请日：2007-06-05

Applicant: Ramesh Gunna ,  Po-Yung Chang ,  Sudarshan Kadambi

Inventor： Ramesh Gunna ,  Po-Yung Chang ,  Sudarshan Kadambi

IPC: G06F11/08

CPC classification number: G06F12/0833 ,  G06F9/3867 ,  G06F12/0862 ,  G06F12/1045 ,  G06F2212/6028

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract translation: 在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。 在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。 在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

公开(公告)号：US20120131281A1

公开(公告)日：2012-05-24

申请号：US13359547

申请日：2012-01-27

Applicant: Ramesh Gunna ,  Sudarshan Kadambi

Inventor： Ramesh Gunna ,  Sudarshan Kadambi

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/126 ,  G06F2212/6028

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract translation: 在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。 在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。 在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

公开(公告)号：US20110047336A1

公开(公告)日：2011-02-24

申请号：US12908535

申请日：2010-10-20

Applicant: Ramesh Gunna ,  Sudarshan Kadambi

Inventor： Ramesh Gunna ,  Sudarshan Kadambi

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0833 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/126 ,  G06F2212/6028

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract translation: 在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。 在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。 在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

公开(公告)号：US07568087B2

公开(公告)日：2009-07-28

申请号：US12055016

申请日：2008-03-25

Applicant: Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

Inventor： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC: G06F7/38 ,  G06F9/00

CPC classification number: G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Abstract translation: 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US20090119488A1

公开(公告)日：2009-05-07

申请号：US12350020

申请日：2009-01-07

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F9/06

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US20080177988A1

公开(公告)日：2008-07-24

申请号：US12055016

申请日：2008-03-25

Applicant: Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

Inventor： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC: G06F9/312

CPC classification number: G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Abstract translation: 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US07376817B2

公开(公告)日：2008-05-20

申请号：US11200744

申请日：2005-08-10

Applicant: Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

Inventor： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Abstract translation: 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US07237096B1

公开(公告)日：2007-06-26

申请号：US10818043

申请日：2004-04-05

Applicant: Julian A. Prabhu ,  Atul Kalambur ,  Sudarshan Kadambi ,  Daniel L. Liebholz ,  Julie M. Staraitis

Inventor： Julian A. Prabhu ,  Atul Kalambur ,  Sudarshan Kadambi ,  Daniel L. Liebholz ,  Julie M. Staraitis

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.

Abstract translation: 如果消费者指令指定由两个32位生产者指令提供的结果组成的64位源寄存器，则可以通过转换一个或多个32位生产者指令来减少每个源寄存器必须跟踪的依赖关系的数量， 简单地将其结果存储在32位目标寄存器中，变换后的指令将其结果存储到64位逻辑寄存器以及另一个32位寄存器中保存的另一个32位值。

公开(公告)号：US20070113020A1

公开(公告)日：2007-05-17

申请号：US11281840

申请日：2005-11-17

Applicant: Ramesh Gunna ,  Sudarshan Kadambi ,  Peter Bannon

Inventor： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter Bannon

IPC: G06F13/28

CPC classification number: G06F12/0808 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0815 ,  G06F2212/507

Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract translation: 在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。 核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。 如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。 另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。 第二个交易与第一笔交易不同。 例如，第二事务可以是无效事务，并且第一事务可以是探查事务。 在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

公开(公告)号：US07996624B2

公开(公告)日：2011-08-09

申请号：US12830630

申请日：2010-07-06

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/12

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个分离的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。