公开(公告)号：US20070113020A1

公开(公告)日：2007-05-17

申请号：US11281840

申请日：2005-11-17

Applicant: Ramesh Gunna ,  Sudarshan Kadambi ,  Peter Bannon

Inventor： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter Bannon

IPC: G06F13/28

CPC classification number: G06F12/0808 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0815 ,  G06F2212/507

Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract translation: 在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。 核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。 如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。 另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。 第二个交易与第一笔交易不同。 例如，第二事务可以是无效事务，并且第一事务可以是探查事务。 在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。