公开(公告)号：US20110264864A1

公开(公告)日：2011-10-27

申请号：US13165297

申请日：2011-06-21

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US07493451B2

公开(公告)日：2009-02-17

申请号：US11453708

申请日：2006-06-15

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US08316188B2

公开(公告)日：2012-11-20

申请号：US13165297

申请日：2011-06-21

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. In an embodiment, the prefetch unit is configured to check for a cache hit for a prefetch request by checking a duplicate cache tags.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。 在一个实施例中，预取单元被配置为通过检查重复的高速缓存标签来检查预取请求的高速缓存命中。

公开(公告)号：US20090119488A1

公开(公告)日：2009-05-07

申请号：US12350020

申请日：2009-01-07

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F9/06

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US07996624B2

公开(公告)日：2011-08-09

申请号：US12830630

申请日：2010-07-06

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/12

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个分离的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US20100268894A1

公开(公告)日：2010-10-21

申请号：US12830630

申请日：2010-07-06

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US07779208B2

公开(公告)日：2010-08-17

申请号：US12350020

申请日：2009-01-07

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US20070294482A1

公开(公告)日：2007-12-20

申请号：US11453708

申请日：2006-06-15

Applicant: Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Abstract translation: 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个分离的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

公开(公告)号：US20070038846A1

公开(公告)日：2007-02-15

申请号：US11200744

申请日：2005-08-10

Applicant: Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

Inventor： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC: G06F9/44

CPC classification number: G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Abstract translation: 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

公开(公告)号：US20090254734A1

公开(公告)日：2009-10-08

申请号：US12486917

申请日：2009-06-18

Applicant: Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

Inventor： Sudarshan Kadambi ,  Po-Yung Chang ,  Eric Hao

IPC: G06F9/312 ,  G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3838

Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

Abstract translation: 在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。 预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。 如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件 操作。 耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。 在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。