公开(公告)号：US20050087837A1

公开(公告)日：2005-04-28

申请号：US10986901

申请日：2004-11-15

Applicant: Mitsuhiro Omura ,  Fumio Sato

Inventor： Mitsuhiro Omura ,  Fumio Sato

IPC: H01L23/522 ,  H01H69/02 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.

Abstract translation: 公开了一种半导体器件，包括半导体衬底，第一金属布线和熔丝，两者都形成在半导体衬底上方相同的水平面上，形成在第一金属布线和熔丝上的第一绝缘膜，第一绝缘膜具有 第一焊盘开口到达第一金属布线，至少形成在第一焊盘开口内的第二金属布线，不在熔丝上方延伸的第二金属布线，形成在第一绝缘膜和第二金属布线上的阻挡膜， 形成在阻挡膜上方的第二绝缘膜。 形成第二焊盘开口以通过去除第二绝缘膜和阻挡膜来露出第二金属布线，通过去除第二绝缘膜和阻挡膜，至少在保险丝上方形成保险丝开口，并且通过去除第一绝缘层 电影不完整。

公开(公告)号：US20120326223A1

公开(公告)日：2012-12-27

申请号：US13344757

申请日：2012-01-06

Applicant: Mitsuhiro Omura

Inventor： Mitsuhiro Omura

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

Abstract translation: 根据一个实施例，一种用于制造半导体存储器件的方法包括：通过交替层叠绝缘膜和导电膜来形成层叠体。 该方法包括在层叠体中形成沟槽。 沟槽沿一个方向延伸并分隔导电膜。 该方法包括在沟槽中埋入二嵌段共聚物。 该方法包括将二嵌段共聚物相分离为多个第一嵌段和沿绝缘膜和导电膜的层叠方向延伸的绝缘性第二嵌段。 该方法包括通过去除第一块来形成多个孔。 该方法包括在孔的内表面上形成电荷累积层。 并且，该方法包括通过将半导体材料埋入孔而形成沿堆叠方向延伸的多个半导体柱。

公开(公告)号：US20120021605A1

公开(公告)日：2012-01-26

申请号：US13013380

申请日：2011-01-25

Applicant: Mitsuhiro OMURA ,  Yumi Ohno ,  Takaya Matsushita ,  Tokuhisa Ohiwa

Inventor： Mitsuhiro OMURA ,  Yumi Ohno ,  Takaya Matsushita ,  Tokuhisa Ohiwa

IPC: H01L21/475 ,  H01L21/4757

CPC classification number: H01L21/31116 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract translation: 在根据一个实施例的半导体器件制造方法中，在半导体衬底上形成含有硅的绝缘膜，在绝缘膜上沉积抗蚀剂，将抗蚀剂图案化成预定图案，并且通过干燥 蚀刻处理，其中使用含有C，F，Br，H和O的气体，其中具有预定图案的抗蚀剂作为掩模。 在抗蚀剂上制造其中C和Br连接的沉积膜。

公开(公告)号：US07943522B2

公开(公告)日：2011-05-17

申请号：US12926135

申请日：2010-10-27

Applicant: Mitsuhiro Omura

Inventor： Mitsuhiro Omura

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01J37/32091 ,  H01J37/32174 ,  H01J2237/334

Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and stopping application of one of the high-frequency powers, thereby reducing a bias voltage generated to the substrate while introducing a second gas after the first dry etching processing to remove a fluorocarbon-based deposition in the reaction chamber and perform a second dry etching processing with respect to the substrate.

公开(公告)号：US20100207240A1

公开(公告)日：2010-08-19

申请号：US12545702

申请日：2009-08-21

Applicant: Junichi Hashimoto ,  Mitsuhiro Omura

Inventor： Junichi Hashimoto ,  Mitsuhiro Omura

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/11578 ,  H01L27/0688 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.

Abstract translation: 半导体器件包括：具有多个导电层和交替层叠的多个电介质层的层叠体，所述层叠体包括具有加工成阶梯形状的多个导电层的阶梯结构; 覆盖所述楼梯结构的层间绝缘层; 以及接触电极，其设置在穿过所述层间电介质层的接触孔内部，所述接触孔穿透所述阶梯状导电层之一，所述接触电极与所述一个所述阶梯状导电层的侧壁部分接触 暴露在接触孔中。

公开(公告)号：US20100176440A1

公开(公告)日：2010-07-15

申请号：US12615120

申请日：2009-11-09

Applicant: Mitsuhiro OMURA

Inventor： Mitsuhiro OMURA

IPC: H01L29/792 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L27/11578 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.

Abstract translation: 半导体器件包括：第一层; 第二层; 柱状结构单元; 和侧部。 第二层设置在第一层的主表面上。 柱状结构单元是导电的并且在第一层和第二层中对准以通过主表面。 侧面部分被添加到主表面的第二层侧上的柱状结构单元的侧壁。

公开(公告)号：US07749913B2

公开(公告)日：2010-07-06

申请号：US12336348

申请日：2008-12-16

Applicant: Mitsuhiro Omura ,  Keisuke Kikutani ,  Yutaka Okamoto

Inventor： Mitsuhiro Omura ,  Keisuke Kikutani ,  Yutaka Okamoto

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138

Abstract: A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.

Abstract translation: 形成第一含硅膜，有机材料膜，第二含硅膜。 将第二含硅膜图案化为具有窄的宽度图案和宽的宽度图案。 有机材料膜被图案化以具有窄的宽度图案和宽的宽度图案。 通过涂覆第三含硅膜，在第二含硅膜和有机材料膜的侧表面上形成侧壁。 通过使用覆盖图案化的第二含硅膜具有宽幅图案和侧壁的掩模来除去第二含硅膜的窄幅图案。 最后，除去有机材料膜。

公开(公告)号：US20090096007A1

公开(公告)日：2009-04-16

申请号：US12244523

申请日：2008-10-02

Applicant: Mitsuhiro OMURA ,  Satoshi NAGASHIMA ,  Katsunori YAHASHI ,  Jungo INABA ,  Daina INOUE

Inventor： Mitsuhiro OMURA ,  Satoshi NAGASHIMA ,  Katsunori YAHASHI ,  Jungo INABA ,  Daina INOUE

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract translation: 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US20080070328A1

公开(公告)日：2008-03-20

申请号：US11889292

申请日：2007-08-10

Applicant: Mitsuhiro Omura

Inventor： Mitsuhiro Omura

IPC: H01L21/00

CPC classification number: H01L29/6656 ,  H01L22/20 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a film to be processed having a first film thickness on a semiconductor substrate; forming a region, within the film to be processed, having a second film thickness thinner than the first film thickness by processing a part of the film to be processed; processing the film to be processed having the region of the second film thickness formed therein by utilizing a dry etching method while a change in characteristic value of a plasma is monitored; detecting a first timing at which a member right under the region, within the film to be processed, which had the second film thickness before the processing performed by utilizing the dry etching method begins to be exposed in accordance with the change in characteristic value of the plasma during the processing performed by utilizing the dry etching method; and estimating a second timing right before a member right under a region, of the film to be processed, which had the first film thickness before the processing performed by utilizing the dry etching method begins to be exposed in accordance with the first timing, and changing an etching condition for the dry etching over to another one at the second timing.

Abstract translation: 根据本发明实施例的制造半导体器件的方法包括：在半导体衬底上形成具有第一膜厚度的被处理膜; 通过加工一部分待处理的膜，在待处理的膜内形成具有比第一膜厚度薄的第二膜厚的区域; 通过利用干蚀刻方法处理其中形成有第二膜厚度的区域的待处理膜，同时监测等离子体的特性值的变化; 检测在通过利用干蚀刻方法进行的处理之前具有第二膜厚度的区域内的区域内的正下方的部件的第一定时开始根据所述干法蚀刻方法的特性值的变化而暴露 在利用干蚀刻方法进行的处理期间的等离子体; 并且在通过利用干法蚀刻方法进行的处理之前具有第一膜厚的区域之下的正在成像的区域之前的第二定时开始根据第一定时曝光，并且改变 用于在第二定时干蚀刻到另一个的蚀刻条件。

公开(公告)号：US20060057828A1

公开(公告)日：2006-03-16

申请号：US11220687

申请日：2005-09-08

Applicant: Mitsuhiro Omura ,  Nobuaki Yasutake

Inventor： Mitsuhiro Omura ,  Nobuaki Yasutake

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/28035 ,  H01L21/76826 ,  H01L21/76834 ,  H01L29/66628 ,  H01L29/7834

Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.

Abstract translation: 公开了一种制造半导体器件的方法，该方法包括在半导体衬底的主表面上形成栅极结构，其间插入栅极绝缘膜，形成第一绝缘膜以覆盖栅极结构和主表面的顶表面和侧表面 的半导体衬底，通过使用不含氟的气体的各向异性等离子体处理覆盖栅极结构的顶表面和半导体衬底的主表面的第一绝缘膜的重整部分，以及去除第一绝缘体的重整部分 电影。