公开(公告)号：US20100132889A1

公开(公告)日：2010-06-03

申请号：US12698406

申请日：2010-02-02

申请人： Kyeong-Koo CHI ,  Erik A. Edelberg

发明人： Kyeong-Koo CHI ,  Erik A. Edelberg

IPC分类号： C23F1/08

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76816

摘要： A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.

摘要翻译： 提供了一种通过碳基掩模蚀刻介电层中的超高宽比特征的方法。 相对于碳基掩模选择性地蚀刻电介质层，其中选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。 选择性蚀刻停止。 相对于碳基掩模选择性地除去氟碳聚合物，使得使用修整保留碳基掩模。 停止选择性除去氟碳聚合物。 相对于碳基掩模再次选择性地蚀刻介电层，其中第二选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。

公开(公告)号：US07547636B2

公开(公告)日：2009-06-16

申请号：US11671342

申请日：2007-02-05

申请人： Kyeong-Koo Chi ,  Erik A. Edelberg

发明人： Kyeong-Koo Chi ,  Erik A. Edelberg

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.

摘要翻译： 提供了一种通过蚀刻室中的基于碳的掩模来选择性地蚀刻超高宽比特征介电层的方法。 提供蚀刻气体的流动，其包括含氟碳分子和含氧分子到蚀刻室。 提供脉冲偏置RF信号。 提供激励RF信号以将蚀刻气体转换成等离子体。

公开(公告)号：US07479445B2

公开(公告)日：2009-01-20

申请号：US11247937

申请日：2005-10-11

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC分类号： H01L21/28 ,  H01L21/335

CPC分类号： H01L29/1037 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/76

摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。 通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。 沟槽填充有栅电极。 第一电绝缘层在含有氧的环境中被图案化。 当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

公开(公告)号：US07384843B2

公开(公告)日：2008-06-10

申请号：US11260377

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

摘要翻译： 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

公开(公告)号：US07291531B2

公开(公告)日：2007-11-06

申请号：US11048995

申请日：2005-02-02

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US07256143B2

公开(公告)日：2007-08-14

申请号：US11058670

申请日：2005-02-15

申请人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

发明人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC分类号： H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

摘要翻译： 提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。 半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。 在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。 第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部 导电层的表面。 第一间隔件包围第一层间绝缘层上的覆盖层的外表面。 第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。 接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与 盖层

公开(公告)号：US20060293781A1

公开(公告)日：2006-12-28

申请号：US11510987

申请日：2006-08-28

申请人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

发明人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

IPC分类号： G06F19/00

CPC分类号： H01L21/67253 ,  H01L21/32137 ,  H01L21/67069 ,  H01L22/20

摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

申请人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

摘要翻译： 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US07125766B2

公开(公告)日：2006-10-24

申请号：US11062546

申请日：2005-02-23

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855

摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

摘要翻译： 公开了一种形成用于半导体器件的电容器的方法。 根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。 各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽 比通过氧化物层的开口的至少一部分。 因此，模具层用于形成具有比其上部宽的下部的存储电极。

公开(公告)号：US07118926B2

公开(公告)日：2006-10-10

申请号：US10652403

申请日：2003-08-29

申请人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

发明人： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

IPC分类号： H01L21/00

CPC分类号： H01L21/67253 ,  H01L21/32137 ,  H01L21/67069 ,  H01L22/20

摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

摘要翻译： 一种优化干蚀刻工艺调味配方的方法。 该方法包括设置重现性的临界值，主蚀刻配方和初步调味配方。 然后使用干蚀刻室中的初步调味配方蚀刻测试晶片。 接下来，使用主蚀刻配方对干蚀刻室中的至少10个运行晶片执行主蚀刻处理，并且确定每个晶片的终点检测时间。 然后使用确定的终点检测时间确定初始色散和标准偏差。 然后将重现性的临界值与初始色散进行比较。 如果初始分散度等于或小于再现性的临界值，则使用初步调味配方作为调味配方，否则初步调味配方被修改，重复该过程直到确定最佳调味配方。