公开(公告)号：US20110237037A1

公开(公告)日：2011-09-29

申请号：US13151494

申请日：2011-06-02

申请人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

摘要翻译： 在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。 可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。 可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。 可以在栅极氧化物层上形成栅电极以填充凹部。 源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。 因此，氧化物层可以具有均匀的厚度分布和致密结构。

公开(公告)号：US07968442B2

公开(公告)日：2011-06-28

申请号：US12459660

申请日：2009-07-06

申请人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

发明人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

IPC分类号： H01L21/28

CPC分类号： H01L29/7854 ,  H01L29/66795

摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

摘要翻译： 翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。 鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。 形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过 栅电极。

公开(公告)号：US20100109057A1

公开(公告)日：2010-05-06

申请号：US12459660

申请日：2009-07-06

申请人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

发明人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7854 ,  H01L29/66795

摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

摘要翻译： 翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。 鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。 形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过 栅电极。

公开(公告)号：US20100035425A1

公开(公告)日：2010-02-11

申请号：US12536865

申请日：2009-08-06

申请人： Jeong Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

发明人： Jeong Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

IPC分类号： H01L21/28 ,  H01L21/283

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。 可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。 然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。 在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

公开(公告)号：US20100025749A1

公开(公告)日：2010-02-04

申请号：US12534422

申请日：2009-08-03

申请人： Jong-Ryeol Yoo ,  Tai-Su Park ,  Jong-Hoon Kang ,  Dong-Chan Kim ,  Jeong-Do Ryu ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin

发明人： Jong-Ryeol Yoo ,  Tai-Su Park ,  Jong-Hoon Kang ,  Dong-Chan Kim ,  Jeong-Do Ryu ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin

IPC分类号： H01L27/10 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L27/10873 ,  H01L27/10894

摘要： A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer

摘要翻译： 半导体器件可以包括隔离层，栅电极，绝缘中间层，杂质区，封盖层和插塞。 隔离层可以形成在衬底中。 栅电极可以形成在衬底上。 绝缘中间层可以形成在栅电极上。 绝缘中间层可以在栅电极之间具有接触孔。 杂质区域可能在通过接触孔暴露的衬底中。 覆盖层可以在杂质区上。 插头可能在封盖层上。 因此，杂质可能不会从杂质区域中流失。 结果，由于在电极层中可能不产生耗尽，所以器件可能具有改善的电特性和可靠性