公开(公告)号：US06538866B1

公开(公告)日：2003-03-25

申请号：US09526737

申请日：2000-03-16

Applicant: Keiji Hanzawa ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Hiromichi Yamada ,  Kohei Sakurai ,  Atsushi Miyazaki

Inventor： Keiji Hanzawa ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Hiromichi Yamada ,  Kohei Sakurai ,  Atsushi Miyazaki

IPC: H02H900

CPC classification number: H01L27/0251 ,  H02H9/04

Abstract: A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.

Abstract translation: 可以通过MOS晶体管制造工艺将用于保护负载的过电压的电路与负载集成在同一芯片上。 该过电压保护电路由浪涌保护电路，过电压检测电路和开关电路构成。 包括两个MOS晶体管的浪涌保护电路工作，借助于两个MOS晶体管的源极 - 漏极击穿电压来钳位施加到电源接收端的浪涌电压，从而吸收浪涌能量。 包括两个MOS晶体管的过电压检测电路进行工作，从而以两个MOS晶体管的源极 - 漏极电压作为参考电压来监视从浪涌保护电路提供的直流电压，从而检测过电压。 过电压检测输出使开关电路的MOS晶体管成为关断状态，以保护负载。

公开(公告)号：US06239628B1

公开(公告)日：2001-05-29

申请号：US09245897

申请日：1999-02-08

Applicant: Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

Inventor： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

IPC: H04L700

CPC classification number: G06F9/3869

Abstract: A semiconductor integrated circuit device is dislosed for self-monitoring presence/absence of a data flow and transmitting the data on the basis of the result of the monitoring. The semiconductor integrated circuit device comprises a plurality of data paths each further comprising at least two logic-circuit blocks. One of the data paths have data-arrival detector for detecting arrival of data and components on the other data paths operate synchronously with those on the data path having the data-arrival detector.

Abstract translation: 半导体集成电路装置被断开，用于自我监测数据流的存在/不存在，并且基于监视结果发送数据。 半导体集成电路装置包括多个数据路径，每个数据路径还包括至少两个逻辑电路块。 数据路径之一具有数据到达检测器，用于检测其他数据路径上的数据和组件的到达与具有数据到达检测器的数据路径上的数据到达检测器同步操作。

公开(公告)号：US5848238A

公开(公告)日：1998-12-08

申请号：US778685

申请日：1997-01-03

Applicant: Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

Inventor： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

IPC: G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F13/00 ,  G06F15/78

CPC classification number: G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

公开(公告)号：US5841300A

公开(公告)日：1998-11-24

申请号：US838193

申请日：1997-04-16

Applicant: Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

Inventor： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

IPC: H03K19/003 ,  H03K19/096

CPC classification number: H03K19/00338

Abstract: The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.

Abstract translation: 本发明旨在提供一种传统的电路设备，其高度耐受噪声并且以比完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，根据本发明的电路装置设置有多个串联的CMOS静态逻辑电路和电位设置装置，其连接到这些逻辑电路的输出部分并将输出部分的输出设置为 与时钟信号同步的低电平，从而通过NMOS电路的操作来传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，电路操作加快，可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。

公开(公告)号：US5313116A

公开(公告)日：1994-05-17

申请号：US765018

申请日：1991-09-24

Applicant: Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

Inventor： Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H01L29/732 ,  H03K17/04 ,  H03K17/16 ,  H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/01

CPC classification number: H01L27/0623 ,  H03K19/001 ,  H03K19/00353 ,  H03K19/09448

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.

Abstract translation: 提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管 耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径 的双极晶体管。 还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路 输出端子和第二电源端子。 为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子 以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

公开(公告)号：US5059821A

公开(公告)日：1991-10-22

申请号：US649854

申请日：1991-02-01

Applicant: Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

Inventor： Fumio Murabayashi ,  Yoji Nishio ,  Shoichi Kotoku ,  Kozaburo Kurita ,  Kazuo Kato

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H01L29/732 ,  H03K17/04 ,  H03K17/16 ,  H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944

CPC classification number: H01L27/0623 ,  H03K19/001 ,  H03K19/00353 ,  H03K19/09448

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.

Abstract translation: 提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。 逻辑电路包括双极晶体管，其具有耦合在第一电源端子和输出端子之间的基极和集电极 - 发射极电流路径，以及至少一个场效应晶体管，其栅极响应于施加到输入端子的输入信号 并且其源极 - 漏极电流路径耦合在第一电源端子和双极晶体管的基极之间。 还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路 输出端子和第二电源端子。 为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子 以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

公开(公告)号：US20090115506A1

公开(公告)日：2009-05-07

申请号：US12345049

申请日：2008-12-29

Applicant: Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

Inventor： Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

IPC: H03F1/50

CPC classification number: H01L21/76283 ,  G05B19/0428 ,  G05B2219/25428 ,  G05B2219/25462 ,  H01L27/0629 ,  H04L25/0266

Abstract: A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pulse signal, which has propagated through an insulating circuit, into the original state signal or a signal having the same characteristics as the original state signal.

Abstract translation: 第一转换器电路将预定时间段内的电平恒定或缓慢变化的状态信号转换成脉冲信号，以允许信号通过电绝缘区域传播。 第二转换器电路将已经通过绝缘电路传播的脉冲信号转换成原始状态信号或具有与原始状态信号相同特性的信号。

公开(公告)号：US07260657B2

公开(公告)日：2007-08-21

申请号：US10491285

申请日：2001-10-02

Applicant: Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Keiji Hanzawa ,  Hiroyasu Sukesako

Inventor： Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Keiji Hanzawa ,  Hiroyasu Sukesako

IPC: G06F3/00 ,  G06F5/00

CPC classification number: H04L7/10 ,  H04J3/24 ,  H04J7/00 ,  H04L7/046 ,  H04L7/06

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.

Abstract translation: 主单元向从单元发送启动信号。 当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号） 。 主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。 响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。 因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。 实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

公开(公告)号：US20060208693A1

公开(公告)日：2006-09-21

申请号：US11375073

申请日：2006-03-15

Applicant: Akihiko Emori ,  Youhei Kawahara ,  Hirotaka Takahashi ,  Fumio Murabayashi ,  Tokiyoshi Hirasawa ,  Tetsuro Okoshi

Inventor： Akihiko Emori ,  Youhei Kawahara ,  Hirotaka Takahashi ,  Fumio Murabayashi ,  Tokiyoshi Hirasawa ,  Tetsuro Okoshi

IPC: H02J7/00

CPC classification number: H02J7/0047 ,  G01R31/006 ,  G01R31/3648 ,  G01R31/371 ,  G01R31/379 ,  G01R31/392

Abstract: The aim of the invention is to provide a battery controller which is able to secure the number of rewrite time as required without replacement. The battery controller including a plurality of memory groups 104a to 104n comprising nonvolatile memories rewritable on the basis of one unit or plural units, a switch for selecting a memory group and a reader/writer 102 for writing or reading data into or from the memory groups, wherein the switch selects sequentially a memory group, according to a signal for writing from outside.

Abstract translation: 本发明的目的是提供一种电池控制器，其能够在不需要更换的情况下保证所需的重写时间。 电池控制器包括多个存储器组104a至104n，包括基于一个单元或多个单元可改写的非易失性存储器，用于选择存储器组的开关和用于将数据写入或读取数据的读取器/写入器102 存储器组，其中所述开关根据从外部写入的信号顺序地选择存储器组。

公开(公告)号：US06999855B2

公开(公告)日：2006-02-14

申请号：US10428802

申请日：2003-05-05

Applicant: Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

Inventor： Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

IPC: G06F7/00

CPC classification number: B60W50/00 ,  B60T8/885 ,  B60T2270/406 ,  B60W50/0205 ,  B60W2050/0006 ,  F02D41/22 ,  F02D41/266 ,  F02D41/3005 ,  F02D2400/18

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have a independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

Abstract translation: 低成本车辆控制系统和使用该系统的汽车控制致动器驱动器的辐射，从而降低辐射部件成本，并允许电子控制单元的小型化以提高通用性。 车辆控制系统具有电子控制单元，用于在致动器侧驱动致动器的多个致动器和致动器驱动器。 致动器驱动器分别具有独立的自诊断部分，自保护部分和通信控制部分，并且相应地分散到致动器。