公开(公告)号：US20030001645A1

公开(公告)日：2003-01-02

申请号：US10175423

申请日：2002-06-19

发明人： Mukesh Nair

IPC分类号： H03K003/037

CPC分类号： H03K3/3565 ,  H03K3/012 ,  H03K17/08122

摘要： A multiple voltage environment input pad with a circuit input comprises a level shifter circuit (A) and a buffer circuit (B). The buffer circuit B comprises an inverter comprising at least two transistors (6, 7) of opposite types, followed by twin controllable voltage dividers (8, 10; 4, 5, 9) of opposite types. Each controllable voltage divider (8, 10; 4, 5, 9) has at least two controllable voltage divider inputs and a controllable voltage divider output. For each of the controllable voltage dividers (8, 10; 4, 5, 9) one of the inputs is connected to an output (16) of the level shifter circuit (A) and another one of the inputs is connected to an output (14) of the inverter. For each of the controllable voltage dividers (8, 10; 4, 5, 9) the voltage divider output is connected to a current input connection of a transistor (6, 7) of corresponding type of the inverter. The level shifter circuit (A) comprises a series pass transistor (2) and in parallel thereto a transistorized capacitor (15). Furthermore a transistorized capacitor (18) is connected between the output of the inverter and the output of one of the two controllable voltage dividers (8, 10; 4, 5, 9).

摘要翻译： 具有电路输入的多电压环境输入焊盘包括电平移位器电路（A）和缓冲电路（B）。 缓冲电路B包括具有相反类型的至少两个晶体管（6,7）的逆变器，其后是相反类型的双可控分压器（8,10; 4,5,9）。 每个可控分压器（8,10; 4,5,9）具有至少两个可控分压器输入和可控分压器输出。 对于每个可控分压器（8,10; 4,5,9），其中一个输入端连接到电平移位器电路（A）的输出端（16），另一个输入端连接到输出端 14）。 对于每个可控分压器（8,10; 4,5,9），分压器输出端连接到相应类型的反相器的晶体管（6,7）的电流输入连接。 电平移位器电路（A）包括串联晶体管（2）并且与晶体管电容器（15）并联。 此外，晶体管电容器（18）连接在逆变器的输出端和两个可控分压器（8,10; 4,5,9）中的一个的输出端之间。

公开(公告)号：US20020163374A1

公开(公告)日：2002-11-07

申请号：US10033525

申请日：2001-12-28

申请人： LUCENT TECHNOLOGIES, INC.

发明人： Rajasekhar Pullela ,  Mario Reinhold

IPC分类号： H03K003/037

CPC分类号： H03K3/0231

摘要： A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.

摘要翻译： 在晶体管带宽限制下工作时，具有改进性能的逻辑电路。 特别地，锁存器包括用于接收电压并产生电流输出的时钟导纳级电路，以及有源负载（例如跨阻抗级电路），其连接以接收作为输入的反向导纳的电流输出 并产生电压输出。 两个独立的跨导纳和跨阻抗级可以组合为单个锁存器对。 一个或多个锁存器对可以串联布置为级联链并连接到时钟导通级锁存器的输出电流。

公开(公告)号：US20020163372A1

公开(公告)日：2002-11-07

申请号：US09848165

申请日：2001-05-03

申请人： International Business Machines Corporation

发明人： David William Boerstler ,  Osamu Takahashi

IPC分类号： H03K003/037

CPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/356121

摘要： A latch includes memory and pulldown circuitry coupled to nodes of the memory for pulling one of the nodes down responsive to data. The pulldown circuitry has gating circuitry for gating the pulling down responsive to a clock signal. The latch also has pull up circuitry coupled to the other one of the memory nodes. A first pull up circuitry section is operable to pull the other one of the memory nodes up to a high state responsive to data. The first pull up circuitry section includes second gating circuitry. The second gating circuitry is operable to gate the pulling up of the other one of the memory nodes responsive to a pull up circuitry clock signal. The first pull up circuitry section more quickly pulls up its memory node, so that the two nodes are pulled up and down at more nearly the same time.

摘要翻译： 闩锁包括耦合到存储器的节点的存储器和下拉电路，用于响应于数据拉下节点之一。 下拉电路具有选通电路，用于响应于时钟信号门控下拉。 锁存器还具有耦合到另一个存储器节点的上拉电路。 第一上拉电路部分可操作以响应于数据将存储器节点中的另一个拉到高状态。 第一上拉电路部分包括第二选通电路。 第二选通电路可操作以响应于上拉电路时钟信号来选通存储器节点中的另一个的上拉。 第一个上拉电路部分更快地拉起其存储器节点，使得两个节点在几乎相同的时间被上下拉。

公开(公告)号：US20020101270A1

公开(公告)日：2002-08-01

申请号：US09922764

申请日：2001-08-07

申请人： FUJITSU LIMITED

发明人： Kazunori Nishizono ,  Tatsuo Kumano

IPC分类号： H03K003/037

CPC分类号： H04B10/6933 ,  H03F3/087 ,  H03F3/45973 ,  H03K3/02337 ,  H03K5/007 ,  H03K5/086 ,  H04B10/6911 ,  H04B10/6931

摘要： A current pulse receiving circuit suitable for converting a current pulse converted by a photodetector from a light pulse received in optical communications and outputting a logic level voltage pulse with an accurate pulse width is disclosed. When an output signal from a current-to-voltage converter circuit is detected to have a large amplitude by a large signal detection circuit, an amount of offset cancellation of a DC cancellation circuit is decreased to limit the amplitude of the output signal from the current-to-voltage converter circuit. Since the amplitude of an input signal of an amplifier circuit is limited, tail characteristics at a trailing edge of a pulse are small and an output is provided at an output terminal with an accurate pulse width.

摘要翻译： 公开了一种电流脉冲接收电路，其适用于将由光电检测器转换的电流脉冲从光通信中接收的光脉冲转换并输出具有精确脉冲宽度的逻辑电平电压脉冲。 当通过大信号检测电路检测到来自电流 - 电压转换器电路的输出信号具有大幅度时，减小直流消除电路的偏移消除量，以限制来自电流 - 电压转换器电路的输出信号的幅度 电压转换电路。 由于放大器电路的输入信号的幅度受到限制，所以在脉冲后沿的尾部特性较小，输出端以精确的脉冲宽度提供输出。

公开(公告)号：US20020089363A1

公开(公告)日：2002-07-11

申请号：US09757267

申请日：2001-01-09

申请人： International Business Machines Corporation, Armonk, NY 10504

发明人： John A. Fifield ,  Erik L. Hedberg ,  Claude L. Bertin ,  Nicholas M. van Heel

IPC分类号： H03K003/037

CPC分类号： H03K3/356008 ,  G11C17/18

摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

摘要翻译： 根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。 优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。 可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。 优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。 通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。 特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

公开(公告)号：US20020050846A1

公开(公告)日：2002-05-02

申请号：US09973551

申请日：2001-10-09

发明人： Yu-Wei Lin

IPC分类号： H03K003/037

CPC分类号： H03K5/151

摘要： A method and device for eliminating a time delay of an inverted signal is disclosed. A data signal is fed to a first flip-flop. The data signal is inverted and then the inverted data signal is fed to a second flip-flop. The first and the second flip-flops are triggered simultaneously. Therefore, a first output signal is outputted from the first flip-flop, and a second output signal is outputted from the second flip-flop, wherein the first output signal is an inverted signal of the second output signal without time delay.

摘要翻译： 公开了一种用于消除反相信号的时间延迟的方法和装置。 数据信号被馈送到第一触发器。 数据信号被反相，然后将反相数据信号馈送到第二触发器。 第一个和第二个触发器同时被触发。 因此，从第一触发器输出第一输出信号，从第二触发器输出第二输出信号，其中第一输出信号是第二输出信号的反相信号，而没有时间延迟。

公开(公告)号：US20020043998A1

公开(公告)日：2002-04-18

申请号：US09923608

申请日：2001-08-07

申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.

发明人： Johannes A.C. Misdom ,  Johannes L.M. Verhees ,  Jozef J.M. Hulshof ,  Frank J.P. Van Rens

IPC分类号： H03K003/037

CPC分类号： H03K3/0231 ,  B60Q1/382 ,  H03K17/063 ,  H03K17/284 ,  H03K17/302

摘要： A two-terminal switch circuit (1) for inclusion in series with a load (20) across a voltage supply (63) for periodically energizing the load (20) from the supply (63) comprises a controllable switch (4) connected between the terminals (2,3), a resistance (8) and a capacitor (9) connected in series between the terminals (2,3), and a voltage threshold responsive arrangement (26) the output signal/input signal characteristic of which exhibits hysteresis. The voltage threshold responsive arrangement (26) has a signal input (27) connected to the common point (12) of the resistance (8) and the capacitor (9), and a signal output (28) connected to a control input (13) of the controllable switch (4). A power supply input (29) of the voltage threshold responsive arrangement (26) is also connected to the common point (12) of the resistance (8) and the capacitor (9) so that the voltage threshold responsive arrangement (26) is powered from across the capacitor (9). In operation the threshold responsive arrangement (26) closes the switch (4) when the capacitor (9) has charged to above a first threshold voltage and opens the switch (4) when the capacitor (9) has thereafter discharged to below a second threshold voltage which is lower than the first threshold voltage. The cycle then repeats. The part of the switch circuit (1) which excludes the capacitor (9) may be constructed as a unitary circuit component having three terminals. The load (20) may comprise direction indicator lamps (21, 22, 23, 24) of a road vehicle.

摘要翻译： 与电源（63）上的负载（20）串联并用于从电源（63）周期性地给负载（20）供电的两端开关电路（1）包括可控开关（4），其连接在 端子（2,3），串联连接在端子（2,3）之间的电阻（8）和电容器（9）以及电压阈值响应装置（26），其输出信号/输入信号特性表现出滞后 。 电压阈值响应装置（26）具有连接到电阻（8）和电容器（9）的公共点（12）的信号输入（27）和连接到控制输入端（13）的信号输出（28） ）可控开关（4）。 电压阈值响应装置（26）的电源输入端（29）也连接到电阻（8）和电容器（9）的公共点（12），使得电压阈值响应装置（26）被供电 来自电容器（9）。 在操作中，当电容器（9）已经充电到高于第一阈值电压时，阈值响应装置（26）闭合开关（4），并且当电容器（9）之后放电到低于第二阈值时打开开关（4） 电压低于第一阈值电压。 然后循环重复。 不包括电容器（9）的开关电路（1）的部分可以被构造为具有三个端子的整体电路部件。 负载（20）可以包括道路车辆的方向指示灯（21,22,23,24）。

公开(公告)号：US20010028269A1

公开(公告)日：2001-10-11

申请号：US09840684

申请日：2001-04-20

申请人： Government of the United States of America, National Aeronautics & Space

发明人： Robert L. Shuler JR.

IPC分类号： H03K003/037

CPC分类号： H03K3/356165 ,  H03K3/0375

摘要： A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

摘要翻译： 延迟电路包括具有输入和输出节点的第一网络，具有输入和输出的第二网络，第二网络的输入耦合到第一网络的输出节点。 第一网络和第二网络被配置为使得在第一网络的输入处的毛刺具有标准毛刺时间或更短的大约二分之一的长度不会导致第二网络的输出处的电压交叉 阈值，在第一网络的输入处的毛刺具有大约二分之二和两个标准毛刺时间之间的长度，导致第二网络的输出处的电压跨越阈值小于毛刺的长度，以及 在具有大于大约两个标准毛刺时间的长度的第一网络的输入处的毛刺导致第二网络的输出处的电压大约在毛刺时间内跨越阈值。 一种方法可以减少锁存器对单个事件的影响。 锁存器包括具有输入和输出的门，以及从输出到门的输入的反馈路径。 该方法包括将延迟插入反馈路径并在门中提供延迟。

公开(公告)号：US20040183581A1

公开(公告)日：2004-09-23

申请号：US10801055

申请日：2004-03-16

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Takuya Yasui ,  Yoichi Matsumura

IPC分类号： H03K003/037

CPC分类号： G01R31/318594

摘要： Formerly, in a microfabrication process of a semiconductor integrated circuit, there has been a problem of occurrence of a malfunction of a circuit during a scan test due to a skew resulting from factors, such as manufacturing variation and a delay calculation error, which have not been detected in simulation. In the present invention, for a plurality of flip-flop circuits which configure a scan chain, by arranging a clock circuit for scan which supplies a clock signal during the scan test separately from a clock circuit for normal operation which supplies a clock signal during a normal operation, arranging a lattice-shaped wiring portion for the clock circuit for scan, and supplying the clock signal for scan to each flip-flop circuit from the lattice-shaped wiring portion, generation of the clock skew resulting from the effect of the delay calculation error or the manufacturing variation in the microfabrication process is prevented, thereby preventing the malfunction during the scan test.

摘要翻译： 以前，在半导体集成电路的微细化处理中，存在由于由于诸如制造变化和延迟计算误差等因素而导致的偏斜而在扫描测试期间发生电路故障的问题， 在模拟中被检测到。 在本发明中，对于配置扫描链的多个触发器电路，通过在扫描测试期间布置用于扫描时钟信号的时钟电路，与用于正常操作的时钟电路分开地提供时钟信号，该时钟电路在 为了进行扫描，配置用于时钟电路的格状布线部分，并从晶格状布线部分向每个触发器电路提供扫描时钟信号，产生由延迟效应引起的时钟偏移 计算误差或微细加工过程中的制造变化被阻止，从而防止扫描试验期间的故障。

公开(公告)号：US20040135611A1

公开(公告)日：2004-07-15

申请号：US10695624

申请日：2003-10-28

发明人： Ulf Tohsche

IPC分类号： H03K003/037

CPC分类号： H03K3/012 ,  H03K3/0372

摘要： A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second feedback loop, where the first and second feedback loops each have a first node and a second node, where the first holding element is designed such that upon a first clock edge of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node in the first feedback loop, where the first node in the first feedback loop is coupled to the first node in the second feedback loop in order to transfer the signal value which is on the first node in the first feedback loop to the second holding element upon a second clock edge of the clock signal and to output the signal value on the noninverting output, wherein the second node in the first feedback loop is coupled to the second node in the second feedback loop in order to transfer the inverted signal value which is on the second node in the first feedback loop to the second holding element upon the second clock edge of the clock signal, where the second node in the second feedback loop corresponds to the noninverting output and the first node in the second feedback loop corresponds to the inverting output.

摘要翻译： 具有用于施加时钟信号的时钟输入，用于施加数据信号的数据输入，非反相输出和反相输出的触发器，其中触发器具有带有第一反馈回路的第一保持元件和具有第二反馈回路的第二保持元件 反馈回路，其中第一和第二反馈回路各自具有第一节点和第二节点，其中第一保持元件被设计为使得在时钟信号的第一时钟沿，数据信号的逻辑值被转移到第一 保持元件和数据信号的逻辑值在第一反馈回路中的第一节点上可用，其中第一反馈回路中的第一节点耦合到第二反馈回路中的第一节点，以便传送信号值 其在所述时钟信号的第二时钟沿上在所述第一反馈回路中的所述第一保持元件的第一节点上，并且在所述同相输出端上输出所述信号值，其中所述第二节点 在第一反馈回路中耦合到第二反馈回路中的第二节点，以便在时钟信号的第二时钟沿将第一反馈回路中的第二节点上的反相信号值传送到第二保持元件， 其中第二反馈回路中的第二节点对应于非反相输出，并且第二反馈回路中的第一节点对应于反相输出。