公开(公告)号：US20020163374A1

公开(公告)日：2002-11-07

申请号：US10033525

申请日：2001-12-28

申请人： LUCENT TECHNOLOGIES, INC.

发明人： Rajasekhar Pullela ,  Mario Reinhold

IPC分类号： H03K003/037

CPC分类号： H03K3/0231

摘要： A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.

摘要翻译： 在晶体管带宽限制下工作时，具有改进性能的逻辑电路。 特别地，锁存器包括用于接收电压并产生电流输出的时钟导纳级电路，以及有源负载（例如跨阻抗级电路），其连接以接收作为输入的反向导纳的电流输出 并产生电压输出。 两个独立的跨导纳和跨阻抗级可以组合为单个锁存器对。 一个或多个锁存器对可以串联布置为级联链并连接到时钟导通级锁存器的输出电流。