公开(公告)号：US20040196082A1

公开(公告)日：2004-10-07

申请号：US10723309

申请日：2003-11-26

申请人： Infineon Technologies AG

发明人： Christian Pacha ,  Roland Thewes ,  Klaus von Amim

IPC分类号： H03K003/037

CPC分类号： H03K3/012 ,  H03K3/356139

摘要： A circuit arrangement comprising a flip-flop, a first power switch transistor, and a plurality of switching transistors. The flip-flop has a plurality of storage transistors with a threshold voltage of a first value. The first power switch transistor has a threshold voltage of a second value, wherein an application of a predetermined electrical potential to its gate terminal brings the circuit arrangement to an operating state such that if at least one supply voltage is switched off, electric charge carriers contained in the circuit arrangement are prevented from flowing away from the circuit arrangement. The plurality of switching transistors, which have a threshold voltage of a third value, are provided between the flip-flop and the first power switch transistor, for coupling a flip-flop input signal into the flip-flop. The magnitude of the first and/or the second value is greater than the magnitude of the third value.

摘要翻译： 一种电路装置，包括触发器，第一功率开关晶体管和多个开关晶体管。 触发器具有多个具有第一值的阈值电压的存储晶体管。 第一功率开关晶体管具有第二值的阈值电压，其中向其栅极端子施加预定电位使得电路装置处于工作状态，使得如果关断至少一个电源电压，则电荷载流子包含 防止电路布置从电路装置流出。 具有第三值的阈值电压的多个开关晶体管设置在触发器和第一功率开关晶体管之间，用于将触发器输入信号耦合到触发器中。 第一和/或第二值的大小大于第三值的大小。

公开(公告)号：US20040150450A1

公开(公告)日：2004-08-05

申请号：US10761753

申请日：2004-01-20

申请人： Linear Technology Corporation

发明人： Karl Edwards

IPC分类号： H03K003/037

CPC分类号： H03K3/012 ,  H03K3/2825 ,  H03K3/288

摘要： A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

摘要翻译： 提供高速，电流驱动的锁存器。 锁存器传导电流并包括输出，SET电路和RESET电路。 输出在第一状态和第二状态之间变化。 SET电路在第一状态下导通锁存器中存在的电流，使得SET电路保持接近将晶体管的输出从第一电平改变到第二电平所需的电平，并且RESET电路在 第二电平使得RESET电路接近将晶体管的输出从第二电平改变到第一电平所需的电平。

公开(公告)号：US20040135610A1

公开(公告)日：2004-07-15

申请号：US10752770

申请日：2004-01-06

发明人： Stephen S. Chang

IPC分类号： H03K003/037

CPC分类号： H03K3/0375 ,  H03K3/012 ,  H03K3/0372 ,  H03K5/133

摘要： A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.

摘要翻译： 第一电路是产生包含数据的数据信号。 第二电路是利用所述数据，其中第一和第二电路通常由锁存信号计时，此外，电路具有第一电平敏感锁存器，以在通过延迟电路接收时锁存来自第一电路的数据信号 锁存信号和第二电平敏感锁存器，以在接收到锁存信号时将第一电平敏感锁存器的输出信号锁存到第二电路。 还描述和要求保护其他实施例。

公开(公告)号：US20040041611A1

公开(公告)日：2004-03-04

申请号：US10649808

申请日：2003-08-28

申请人： Broadcom Corporation

发明人： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC分类号： H03K003/037

CPC分类号： H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

摘要翻译： 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US20040008068A1

公开(公告)日：2004-01-15

申请号：US10452713

申请日：2003-06-02

申请人： Samsung Electronics Co., Ltd.

发明人： Min-su Kim

IPC分类号： H03K003/037

CPC分类号： H03K3/356139

摘要： Provided is a flip-flop capable of operating at high speed by reducing a clock-to-output delay. The flip-flop includes a sense amplifier and a latch circuit. The sense amplifier includes a first node and a second node, precharges the first node and the second node with a supply voltage according to a state of a clock signal, or receives and amplifies differential input signals according to the state of the clock signal, so as to output differential output signals to the first node and the second node. The latch circuit is connected to the first node and the second node, and detects and latches the differential input signals according to the state of the clock signal and the differential output signals. The flip-flop described above does not use a NAND gate, so that a clock-to-output delay can be reduced. Therefore, the flip-flop has an advantage of operating at high speed.

摘要翻译： 提供了能够通过减少时钟到输出延迟而以高速运行的触发器。 触发器包括读出放大器和锁存电路。 读出放大器包括第一节点和第二节点，根据时钟信号的状态对第一节点和第二节点进行预充电，或根据时钟信号的状态接收和放大差分输入信号，因此， 以将差分输出信号输出到第一节点和第二节点。 锁存电路连接到第一节点和第二节点，并根据时钟信号和差分输出信号的状态来检测和锁存差分输入信号。 上述触发器不使用NAND门，从而可以减少时钟到输出的延迟。 因此，触发器具有高速运行的优点。

公开(公告)号：US20030218488A1

公开(公告)日：2003-11-27

申请号：US10444458

申请日：2003-05-23

发明人： Ishwardutt Parulkar ,  Ha M. Pham

IPC分类号： H03K003/037

CPC分类号： G01R31/318536 ,  G01R31/318541

摘要： An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a first scan slave element capable of capturing data on a positive edge of a clock signal; and a second scan slave element capable of capturing data on a negative edge of the clock signal. An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a scan slave element capable of capturing data on either a positive edge or a negative edge of a clock signal; wherein a control signal determines whether the scan slave element captures data on the positive edge or negative edge of the clock signal.

摘要翻译： 扫描具有扫描能力的双边沿触发触发器的装置和方法包括：能够在时钟信号的上升沿捕获数据的第一扫描从属元件; 以及能够在时钟信号的下降沿捕获数据的第二扫描从属元件。 扫描具有扫描能力的双边沿触发触发器的装置和方法包括能够在时钟信号的上升沿或下降沿捕获数据的扫描从属元件; 其中控制信号确定扫描从属单元是否捕获时钟信号的正边缘或负边缘上的数据。

公开(公告)号：US20030102898A1

公开(公告)日：2003-06-05

申请号：US10342045

申请日：2003-01-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H03K003/037

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US20030062938A1

公开(公告)日：2003-04-03

申请号：US10229924

申请日：2002-08-28

发明人： Pietro Piersimoni ,  Pasquale Pistilli ,  Elio D'Ambrosio

IPC分类号： H03K003/037

CPC分类号： G11C16/06

摘要： A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

摘要翻译： 多分区存储器阵列具有用于每个分区的命令用户界面和逻辑接口。 逻辑接口从每个命令用户界面接收信号，以将命令用户界面中的可执行命令限制为在给定每个命令用户界面的当前状态的情况下不会对系统征税的那些命令。

公开(公告)号：US20030042955A1

公开(公告)日：2003-03-06

申请号：US10229162

申请日：2002-08-28

申请人： Kabushiki Kaisha Toshiba

发明人： Atsushi Nakayama ,  Toshimasa Namekawa

IPC分类号： H03K003/037

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  H03K19/00323 ,  H03K19/00369 ,  H03K2005/00123 ,  H03K2005/0013

摘要： An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

摘要翻译： 根据本发明的电子电路包括：第一延迟补偿电路，其接收第一电源电压和第一信号，并输出延迟第一预定时间的第一输出信号;第二延迟补偿电路，其接收第二电源电压;以及 第一信号并输出​​延迟了第二预定时间的第二输出信号;第一逻辑电路，接收从第二延迟补偿电路输出的第一电源电压和第二输出信号，并通过执行第一逻辑运算输出第一运算结果 以及第二逻辑电路，其接收从第一延迟补偿电路输出的第二电源电压和第一输出信号，并通过执行第二逻辑运算输出第二运算结果。

公开(公告)号：US20030025544A1

公开(公告)日：2003-02-06

申请号：US09921471

申请日：2001-08-03

发明人： David Marshall ,  Karl J. Bois ,  David W. Quint

IPC分类号： H03K003/037

CPC分类号： H03K5/08 ,  H04L25/063

摘要： A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

摘要翻译： 将参考电压动态地移动到最后接收的值的电压电平。 移动发生在比特时间的预定分数之内。 移动量受到限制，使得连续的逻辑值不会导致不可用的参考电压电平。 当接收机的输出变化时，状态机将模拟参考电压输入的选择排列到多路复用器，以将输出参考电压移向刚刚接收的值的稳态信号电压电平。 当序列完成时，状态机保持在输出上选择的最后一个值，直到接收器的输出改变值。