公开(公告)号：US06370557B1

公开(公告)日：2002-04-09

申请号：US09326693

申请日：1999-06-07

申请人： Koichi Onuma

发明人： Koichi Onuma

IPC分类号： G06F748

CPC分类号： G06F7/544 ,  G06F7/49994 ,  G06F7/5318

摘要： A processing apparatus capable of reducing the size of the circuit, where in order to perform an operation “(A−B)×C”, provision is made of multiplexers 500 to 5015 provided corresponding to each of all combinations of natural numbers i and j which receive as their inputs bit data Ai, Bi, and Cj, output the bit data Ai when the Cj has the logical value “1”, and output the bit data Biwhen the Cj has the logical value “0”, and the bit data output from the multiplexers 500 to 5015, data obtained by shifting the complement data of 2 of the data B by exactly n bits toward the most significant bit, the data B and the carry data as the carrying from the lower significant bit are added for every bit so as to add the bit data output from the multiplexers 500 to 5015 to the (i+j)th bit.

摘要翻译： 一种能够减小电路尺寸的处理装置，其中为了执行“（AB）xC”的操作，提供对应于自然数i和j的所有组合中的每一个提供的多路复用器500至5015，其接收为 它们的输入位数据Ai，Bi和Cj在Cj具有逻辑值“1”时输出位数据Ai，并且当Cj具有逻辑值“0”时输出位数据Bi，并从 多路复用器500至5015，通过将数据B的2的补码数据精确地移位到最高有效位，将数据B和作为低位有效位的载入的数据B和进位数据移位到每一位， 将从多路复用器500至5015输出的比特数据添加到第（i + j）比特。

公开(公告)号：US06341299B1

公开(公告)日：2002-01-22

申请号：US09253681

申请日：1999-02-19

申请人： Fabrice Romain

发明人： Fabrice Romain

IPC分类号： G06F748

CPC分类号： G06F7/5324 ,  G06F7/5443 ,  G06F7/728

摘要： The computation time of modular operations on large-format data is improved by using a computation circuit integrated as a modular arithmetic coprocessor. The computation circuit carries out an S=A*B+C type operation, with S and C encoded on 2*Bt bits, and A and B encoded on Bt bits. To carry out this operation, a storage flip-flop circuit enables the storage of a possible overflow carry value at the end of an elementary computation, and reinserts this carry value during the following computation.

摘要翻译： 通过使用集成为模数算术协处理器的计算电路，提高了大格式数据模块化操作的计算时间。 计算电路执行S = A * B + C型操作，S和C编码在2 * Bt位上，A和B编码在Bt位上。 为了执行该操作，存储触发器电路能够在基本计算结束时存储可能的溢出进位值，并且在随后的计算期间重新插入该进位值。

公开(公告)号：US06687771B2

公开(公告)日：2004-02-03

申请号：US09769498

申请日：2001-01-26

申请人： Dominic Hugo Symes

发明人： Dominic Hugo Symes

IPC分类号： G06F748

CPC分类号： G06F7/544 ,  G06F5/00 ,  G06F2207/3808

摘要： An input data word contains multiple abutting input data values An. The input data word is split into two intermediate data words into which respective high order portions and low order portions of the data values are written spaced apart by vacant portions. Each intermediate data word may then be subject to one or more data processing operations with bits of the results extending into the vacant portions without corrupting adjacent data values. Finally, the intermediate data words may be recombined to produce result data values.

摘要翻译： 输入数据字包含多个邻接输入数据值An。 输入数据字被分成两个中间数据字，数据值的相应高阶部分和低阶部分被空出部分间隔开。 然后可以对每个中间数据字进行一个或多个数据处理操作，其中结果的比特延伸到空的部分而不破坏相邻的数据值。 最后，中间数据字可以被重组以产生结果数据值。

公开(公告)号：US06578059B1

公开(公告)日：2003-06-10

申请号：US09169669

申请日：1998-10-10

申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

IPC分类号： G06F748

CPC分类号： G06F9/3865 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/49942 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30123 ,  G06F2207/382

摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

公开(公告)号：US06553395B2

公开(公告)日：2003-04-22

申请号：US09997176

申请日：2001-11-28

申请人： Alan David Marshall ,  Anthony Stansfield ,  Jean Vuillemin

发明人： Alan David Marshall ,  Anthony Stansfield ,  Jean Vuillemin

IPC分类号： G06F748

CPC分类号： G06F7/527 ,  G06F7/53 ,  G06F7/5338 ,  G06F9/3017 ,  G06F9/3897 ,  G06F15/7867 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

摘要： The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the processing devices comprises an arithmetic logic unit, which is adapted to perform a function on input operands and produce an output. The input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle. Dynamic instructions are enabled by means provided to route the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.

公开(公告)号：US06519694B2

公开(公告)日：2003-02-11

申请号：US09243982

申请日：1999-02-04

申请人： Jeremy G Harris

发明人： Jeremy G Harris

IPC分类号： G06F748

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3842

摘要： In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose. In other embodiments of the invention, similar functionality is provided for integer registers using poison/valid bits in conjunction with an arithmetic logic unit designed to propagate the poison/valid bits through its operations. An advantage to be gained by this design is that it becomes possible to delay testing the results of a non-faulting load, since the QNaN-like symbolic entity will propagate with the results of operations on an invalid datum, thereby keeping track of the integrity of the data.

摘要翻译： 在支持IEEE 754非数字（NaN）标准和包括加载/存储单元，寄存器单元和算术逻辑单元的类型的RISC或CISC处理器中，并且其中加载/存储单元具有错误标志 为了在已经完成但已导致错误的负载之后标记加载到加载/存储单元的基准，处理器被提供有位模式发生器，其可操作地布置在从加载/存储单元到至少一个 寄存器单元和算术逻辑单元，使得无效数据的非数字值被加载到浮点寄存器或算术逻辑单元中的目的地之一。 算术逻辑单元被配置为通过其操作将Not-a-Number值作为静默非数字（QNaN）值传播。 可以通过为此目的提供的系统软件命令代码在基准面上测试QNaN值。 在本发明的其他实施例中，与使用毒性/有效位结合用于通过其操作来传播毒性/有效位的算术逻辑单元的整数寄存器提供类似的功能。 这种设计可以获得的优点是可以延迟测试非故障负载的结果，因为类似QNaN的符号实体将随着操作结果在无效数据上传播，从而跟踪完整性 的数据。

公开(公告)号：US06512999B1

公开(公告)日：2003-01-28

申请号：US09401184

申请日：1999-09-23

申请人： Athanassios Dimas ,  Isaac Lottati ,  Peter Bernard ,  James Collins ,  James C. Geiger

发明人： Athanassios Dimas ,  Isaac Lottati ,  Peter Bernard ,  James Collins ,  James C. Geiger

IPC分类号： G06F748

CPC分类号： G06T13/20 ,  G06T17/00 ,  G06T2210/24

摘要： In accordance with a preferred embodiment of the invention, a novel apparatus for and method of simulating physical processes such as fluid flow is provided. Fluid flow near a boundary or wall of an object is represented by a collection of vortex sheet layers. The layers are composed of a grid or mesh of one or more geometrically shaped space filling elements. In the preferred embodiment, the space filling elements take on a triangular shape. An Eulerian approach is employed for the vortex sheets, where a finite-volume scheme is used on the prismatic grid formed by the vortex sheet layers. A Lagrangian approach is employed for the vortical elements (e.g., vortex tubes or filaments) found in the remainder of the flow domain. To reduce the computational time, a hairpin removal scheme is employed to reduce the number of vortex filaments, and a Fast Multipole Method (FMM), preferably implemented using parallel processing techniques, reduces the computation of the velocity field.

摘要翻译： 根据本发明的优选实施例，提供了一种用于模拟诸如流体流动之类的物理过程的新型装置和方法。 物体的边界或壁附近的流体流由涡流片层的集合表示。 这些层由一个或多个几何形状的空间填充元件的网格或网格组成。 在优选实施例中，空间填充元件呈三角形。 涡流片采用欧拉方法，其中在由涡旋片层形成的棱镜格栅上使用有限体积方案。 对于在流域的其余部分中发现的涡旋元件（例如，涡流管或细丝）采用拉格朗日方法。 为了减少计算时间，使用发夹去除方案来减少涡流细丝的数量，并且优选地使用并行处理技术实现的快速多极方法（FMM）减少了速度场的计算。

公开(公告)号：US06185593B2

公开(公告)日：2001-02-06

申请号：US09120775

申请日：1998-07-22

申请人： Jeffrey S. Brooks ,  James S. Blomgren

发明人： Jeffrey S. Brooks ,  James S. Blomgren

IPC分类号： G06F748

CPC分类号： G06F5/012 ,  G06F7/483 ,  G06F7/49957

摘要： The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for shifting of the intermediate result prior to normalization or rounding. The exponent is pre-incremented prior to normalization. During normalization, the most significant bit of the intermediate fraction is shifted into the carry bit and the exponent is decremented accordingly. Selection logic then selects one of six possible formatting procedures to generate a mathematically correct output fraction in proper ANSI/IEEE 754-1985 floating point format, and formatting logic generates the output fraction according to the selected formatting procedure.

摘要翻译： 本发明描述了在ANSI / IEEE 754-1985浮点中间结果上执行并行归一化和舍入的方法和装置，其不需要在归一化或舍入之前中间结果的移位。 在归一化之前，指数是预先递增的。 在归一化期间，中间分数的最高有效位被移入进位位，并且指数相应地递减。 选择逻辑然后选择六种可能的格式化过程之一，以适当的ANSI / IEEE 754-1985浮点格式生成数学上正确的输出分数，格式化逻辑根据选择的格式化过程生成输出分数。

公开(公告)号：US06836754B2

公开(公告)日：2004-12-28

申请号：US09774924

申请日：2001-01-31

申请人： John Cooper

发明人： John Cooper

IPC分类号： G06F748

CPC分类号： G05B17/02 ,  G05B15/02

摘要： Disclosed is a safety restraint design controller for controlling the design of a safety restraint system so that a predetermined desired level of an occupant's response (89) is produced. The controller has a database (85) for storing an occupant restraint factor response model (90). The model (90) interrelates at least one predetermined restraint factor (88) with the occupant response (89), the restraint factors having a level that is indicative of setting values for controlling the safety restraint design. A database engine connected to the database (85) determines a level for the occupant response (89) based upon the model and upon a first level of the restraint factors. An optimizer is connected to the database engine for determining a second level of the restraint factors (88), which produces the desired level of the occupant response based upon the desired level of the occupant response (89) from the database engine; whereby the safety restraints design is controlled based upon the determined second level of the restraint factors that produces the desired level of the safety response.

摘要翻译： 公开了一种用于控制安全约束系统的设计的安全约束设计控制器，从而产生预定的乘客响应水平（89）。 控制器具有用于存储乘员约束因子响应模型（90）的数据库（85）。 模型（90）将至少一个预定约束因子（88）与乘员响应（89）相关联，约束因子具有指示用于控制安全限制设计的设定值的水平。 连接到数据库（85）的数据库引擎基于模型和约束因子的第一级确定乘员响应（89）的级别。 优化器连接到数据库引擎，用于确定约束因子（88）的第二级别，其基于来自数据库引擎的所述乘员响应（89）的期望水平产生所述乘员响应的期望水平; 由此基于所确定的产生所需安全响应水平的约束因子的第二级别来控制安全限制设计。

公开(公告)号：US06691075B1

公开(公告)日：2004-02-10

申请号：US09521295

申请日：2000-03-09

申请人： Graham A. Winbow ,  William A. Schneider, Jr.

发明人： Graham A. Winbow ,  William A. Schneider, Jr.

IPC分类号： G06F748

CPC分类号： G01V1/30 ,  G01V1/282 ,  G01V2210/614 ,  G01V2210/66

摘要： A model seismic image of a subsurface seismic reflector is constructed, wherein a set of source and receiver pairs is located, and a subsurface velocity function is determined. Specular reflection points are determined on the subsurface seismic reflector for each of the source and receiver pairs. A Fresnel zone is determined on the subsurface seismic reflector for each of the specular reflection points, using the subsurface velocity function. One or more seismic wavelets are selected and a set of image points is defined containing the subsurface seismic reflector. A synthetic seismic amplitude is determined for each of the image points by summing the Fresnel zone synthetic seismic amplitude for all of the Fresnel zones that contain the image point, using the seismic wavelets. The model seismic image of the subsurface seismic reflector is constructed, using the synthetic seismic amplitudes at the image points.

摘要翻译： 构造了地下地震反射体的地震模型，其中定位了一组源和接收器对，确定了地下速度函数。 对于每个源和接收器对，在地下地震反射器上确定镜面反射点。 使用地下速度函数，在每个镜面反射点的地下地震反射体上确定菲涅耳带。 选择一个或多个地震小波，并且定义包含地下地震反射器的一组图像点。 通过使用地震小波对包含图像点的所有菲涅耳带的菲涅耳带合成地震振幅求和，确定每个图像点的合成地震幅度。 利用图像点的合成地震幅度，构建地下地震反射体的地震模型。