公开(公告)号：US5226003A

公开(公告)日：1993-07-06

申请号：US724820

申请日：1991-07-02

申请人： Masato Nagamatsu

发明人： Masato Nagamatsu

IPC分类号： G06F7/533 ,  G06F7/506 ,  G06F7/52 ,  G06F7/523 ,  G06F7/527

CPC分类号： G06F7/5336

摘要： A low-cost high-speed multiplier comprises a first register for holding a multiplier; a second register for holding a multiplicand; a partial product generator for scanning the multiplier held in the first register to generate three partial products of the multiplicand held in the second register; a 4-input adder for finding the sum of the three partial products and a fourth number; a shift register for holding and shifting the sum; and a unit for returning the shifted sum except a shifted-out portion of the sum to an input of the 4-input adder. This arrangement can process three partial products in one time of addition.

摘要翻译： 低成本高速乘法器包括用于保持乘法器的第一寄存器; 持有被乘数的第二个登记册; 用于扫描保持在第一寄存器中的乘法器的部分乘积发生器，以产生保持在第二寄存器中的被乘数的三个部分乘积; 一个用于找到三个部分乘积和第四个数字的和的4输入加法器; 用于持有和转移总和的移位寄存器; 以及用于将除了移除的和除去的部分之外的移位的和返回到4输入加法器的输入的单元。 这种安排可以在一次添加中处理三种部分产品。

公开(公告)号：US5175862A

公开(公告)日：1992-12-29

申请号：US536197

申请日：1990-06-11

申请人： Andrew E. Phelps ,  Douglas R. Beard ,  Michael A. Woodsmansee

发明人： Andrew E. Phelps ,  Douglas R. Beard ,  Michael A. Woodsmansee

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/483 ,  G06F7/527 ,  G06F7/53 ,  G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F15/173 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F15/8053 ,  G06F15/17381 ,  G06F15/8076 ,  G06F15/8092 ,  G06F17/16 ,  G06F7/00 ,  G06F8/433 ,  G06F8/45 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： A special purpose arithmetic boolean unit is capable of performing extremely parallel bit-level boolean operations, particularly bit matrix manipulations. The special purpose arithmetic boolean unit is especially adapted for use in traditional vector processors, thereby enabling a vector processor to effectively solve extremely parallel MIMD or SIMD boolean problems without requiring an array processor or massively parallel supercomputer.

摘要翻译： 特殊用途算术布尔单元能够执行极其平行的位级布尔运算，特别是位矩阵操作。 专用算术布尔单元特别适用于传统的矢量处理器，从而使矢量处理器能够有效地解决非常平行的MIMD或SIMD布尔问题，而无需阵列处理器或大规模并行超级计算机。

公开(公告)号：US5140545A

公开(公告)日：1992-08-18

申请号：US655316

申请日：1991-02-13

申请人： Stamatis Vassiliadis ,  Josephine A. Boston

发明人： Stamatis Vassiliadis ,  Josephine A. Boston

IPC分类号： G06F7/38 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/533 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： A system for dividing a digital dividend operand N by a digital divisor operand D to obtain a quotient operand Q with minimal execution time and hardware calculates a value NP.sub.0 P.sub.1 . . . P.sub.m, where the value P.sub.0 P.sub.1 . . . P.sub.m has a magnitude such that NP.sub.0 P.sub.1 . . . P.sub.m converges to Q and DP.sub.0 P.sub.1 converges to 1. The divider employs a one's complementation, multiplication and addition sequence to calculate the value NP.sub.0 P.sub.1 . . . P.sub.m.

公开(公告)号：US4994997A

公开(公告)日：1991-02-19

申请号：US245887

申请日：1988-09-16

申请人： Philippe Martin ,  Thierry Bonnet ,  Yves Mathieu

发明人： Philippe Martin ,  Thierry Bonnet ,  Yves Mathieu

IPC分类号： G06F7/527 ,  G06F7/508 ,  G06F7/52 ,  G06F7/525 ,  G06F7/544

CPC分类号： G06F7/5443 ,  G06F7/525 ,  G06F7/5324 ,  G06F2207/3884

摘要： A pipeline-type serial multiplier having a cellular structure, each cell comprising an adder which operates on 3 one-bit data x, y, c and which determines the result v modulo 2 and the carry c.sub.o of the addition of x, y, and c. Each adder simultaneously determines a data c.sub.1 which is the modulo 2 result of the addition of x, y, c.sub.o. This enables the exact final result of a multiplication of a data A of n bits by a data B of p bits to be obtained in two successive segments: a segment L which is formed by the p bits of lowest digital weight and a segment H which is formed by the n bits of the highest weight. The output rate is F/n, where F is the clock frequency. The multiplier circuits can be cascaded under the control of an external signal. They can also be connected in parallel in order to add the results of two multiplications.

摘要翻译： 具有蜂窝结构的流水线型串行乘法器，每个单元包括对3位1位数据x，y，c进行操作的加法器，并且其确定结果v为模2，并且x，y和x的加法的进位co C。 每个加法器同时确定作为x，y，co的相加的模2结果的数据c1。 这使得能够在两个连续的段中获得n位的数据A乘以p位的数据B的精确最终结果：由最低数字权重的p位形成的段L和段H 由最高重量的n位形成。 输出速率为F / n，其中F为时钟频率。 乘法器电路可以在外部信号的控制下级联。 它们也可以并联连接，以增加两次乘法的结果。

公开(公告)号：US4769779A

公开(公告)日：1988-09-06

申请号：US809352

申请日：1985-12-16

申请人： Christopher T. Chang ,  Granville E. Ott

发明人： Christopher T. Chang ,  Granville E. Ott

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52 ,  G06F7/523 ,  G06F7/527 ,  G06F7/533 ,  G06F17/14 ,  G06F15/332 ,  G06F15/347

CPC分类号： G06F17/142

摘要： A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operations. A ROM (12) provides the multipliers for the operation which are input to a booth decoder (50) through a delay line (48). The delay line (48) delays pairs of bits by one bit each to synchronize with the flow of the partial products through the array (26). After one product is processed in the array (26), the sum and carry is fed back to the input through a delay (52). This delay allows for processing two products in a single operation with a subsequent operation interleaved therebetween. When one operation is complete, it is output to adders (64) and (66) to perform a complex addition and substraction with another input data vector. This addition occurs at one half the rate of the pipeline (26) due to the interleaving of the two operations.

摘要翻译： 复数乘法器包括乘法器单元的进位和收缩阵列（26），用于根据经修改的布斯算法处理被乘数的乘法器单元。 乘法器执行两次乘法和两次加法/减法运算。 ROM（12）通过延迟线（48）提供输入到展台解码器（50）的操作的乘法器。 延迟线（48）将每比特的比特延迟一位以与通过阵列（26）的部分乘积的流同步。 在阵列（26）中处理一个产品之后，通过延迟（52）将和和进位反馈到输入。 该延迟允许在单个操作中处理两个产品，随后在其间交错的操作。 当一个操作完成时，它被输出到加法器（64）和（66）以执行与另一个输入数据向量的复数加法和减法。 由于两个操作的交错，这种加法以管线（26）的一半速率发生。

公开(公告)号：US4683547A

公开(公告)日：1987-07-28

申请号：US664739

申请日：1984-10-25

申请人： Richard D. DeGroot

发明人： Richard D. DeGroot

IPC分类号： G06F7/487 ,  G06F7/00 ,  G06F7/527 ,  G06F7/544 ,  G06F7/57 ,  G06F7/76 ,  G06F9/302 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F7/5443 ,  G06F7/483 ,  G06F9/3001 ,  G06F2207/3884

摘要： A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/divide operation on a bypass bus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

摘要翻译： 一种数据处理系统包括具有放弃和旁路总线的多个浮点运算单元，其包括用于处理多个乘法或除法指令的新指令。 这些指令通过加法操作分开，包括将旁路总线上的每个乘法/除法运算的结果与来自加法器输出的累加旁路总线的输入一起传递给加法器的输入，该旁路总线是加法器的输出，用于自动添加操作 累积乘法或累加除法运算。 这允许每个周期产生两个浮点结果，其中一个可以在没有中央解码器的任何中间控制的情况下累积。 累加在累加器逻辑本身的分布式控制下执行。

公开(公告)号：US4555769A

公开(公告)日：1985-11-26

申请号：US498214

申请日：1983-05-25

申请人： Eric L. Carter ,  Harold T. Ward

发明人： Eric L. Carter ,  Harold T. Ward

IPC分类号： G06F7/72 ,  G06F7/38 ,  G06F7/527 ,  G06F7/53 ,  H03M7/18

CPC分类号： H03M7/18

摘要： A modular modulus-N residue circuit apparatus uses cascode logic networks in the modules for generating greater than one odd integer N residues.

摘要翻译： 模块模数N残余电路装置在模块中使用共源共栅逻辑网络来产生大于一个奇数整数N个残差。

公开(公告)号：US4543641A

公开(公告)日：1985-09-24

申请号：US461257

申请日：1983-01-26

申请人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

发明人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

IPC分类号： G06F7/53 ,  G06F7/491 ,  G06F7/496 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/4915

摘要： A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.

摘要翻译： 一种乘法器装置，包括用于保持加法结果的保持装置，用于产生每个具有2n位的k个块产物的块产生装置，其中n是等于或大于2的整数，所述k个块产物通过将每个块乘以n 比特，k个块通过以被乘数的最低有效位的n比特的间隔划分被乘数而获得，以及加法器装置，用于将两组块产物加到保持装置的输出，两组块产物由 替代块产品从块产品中获取块产品的手段。

公开(公告)号：US4272827A

公开(公告)日：1981-06-09

申请号：US21011

申请日：1979-03-16

申请人： Norio Inui ,  Noriaki Kume ,  Tetsuro Okamoto

发明人： Norio Inui ,  Noriaki Kume ,  Tetsuro Okamoto

IPC分类号： G06F7/52 ,  G06F7/527 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

摘要翻译： 分割处理系统通过有效地使用N位精度的分割处理电路来执行2N位精度分割处理。 系统以2N位精度进行除法，如下所示：（n = N：选定二进制数A，B，C和D中的位数）。 上述表达式近似为Q1 + Q2x2-n（Q1，Q2：二进制数）的形式。 二进制数Q1和Q2分别由具有N位精度的分割处理电路操作。 通过有效控制，在Q1的分割处理期间引起的误差被用作执行Q2的分割处理的数据的一部分，从而有效地将在Q1处理期间发生的任何错误转移到Q2。 该功能在仅具有四个寄存器，N位容量（精度）和操作寄存器，乘法电路，分频电路和移位电路的系统中执行，从而提供对寄存器之间的数据传输的适当控制。

公开(公告)号：US4173789A

公开(公告)日：1979-11-06

申请号：US865211

申请日：1977-12-28

申请人： Haruhisa Miura

发明人： Haruhisa Miura

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/5334

摘要： A multiplication control system comprising a multiplying circuit to which a binary-coded multiplier and a binary-coded multiplicand are supplied, a leading 0/1 decoder which detects the number of significant digits in the binary-coded multiplier, a divider which divides the detected decoder output by a predetermined number, a selector into which an external constant is entered, a recursive control counter to which an output of the selector is supplied, an arithmetic unit which calculates the difference of outputs from said divider and said counter, a zero detector which detects the content "zero " of said recursive control counter, a shift circuit to which a product of said multiplying circuit controlled by the zero detector output is transmitted, and a multiplier which multiplies the output of said divider by a predetermined number and supplies the result to said shifter.

摘要翻译： 一种乘法控制系统，包括被提供二进制编码乘法器和二进制编码乘法器的乘法电路，检测二进制编码乘法器中的有效数位数的前导0/1解码器，分频器 输出预定数量的解码器，输入外部常数的选择器，提供选择器的输出的递归控制计数器，计算所述分频器和所述计数器的输出差的运算单元，零检测器 其检测所述递归控制计数器的内容“零”，发送由零检测器输出控制的所述乘法电路的乘积的移位电路和将所述除法器的输出乘以预定数量的乘法器， 导致所述移位器。