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1.发明授权
公开(公告)号：US5852728A
公开(公告)日：1998-12-22
申请号：US585344
申请日：1996-01-11
申请人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
发明人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1679 , G06F11/20
摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.
摘要翻译： 本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。 在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此 在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。 设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。
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公开(公告)号：US4543641A
公开(公告)日：1985-09-24
申请号：US461257
申请日：1983-01-26
申请人： Masaharu Fukuta , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki
发明人： Masaharu Fukuta , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki
CPC分类号： G06F7/4915
摘要： A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.
摘要翻译： 一种乘法器装置，包括用于保持加法结果的保持装置，用于产生每个具有2n位的k个块产物的块产生装置，其中n是等于或大于2的整数，所述k个块产物通过将每个块乘以n 比特，k个块通过以被乘数的最低有效位的n比特的间隔划分被乘数而获得，以及加法器装置，用于将两组块产物加到保持装置的输出，两组块产物由 替代块产品从块产品中获取块产品的手段。
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公开(公告)号：US4603397A
公开(公告)日：1986-07-29
申请号：US462423
申请日：1983-01-31
申请人： Toru Ohtsuki , Yoshio Oshima , Sako Ishikawa , Masaharu Fukuta
发明人： Toru Ohtsuki , Yoshio Oshima , Sako Ishikawa , Masaharu Fukuta
CPC分类号： G06F7/4917
摘要： In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.
摘要翻译： 在用二进制编码的十进制数分割方案中使用的商数预测表的地址和二进制编码十进制表示中的除数的除数和除数的二进制编码的十进制数分割方案中，地址被修改。 因此，地址的绝对位数减少，从而可以显着地减少用于实现商预测表所需的RAM的数据量和因此的容量，同时确保商预测表的令人满意的功能。 用于二进制编码的十进制数除法的装置以小尺寸廉价地实现。
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公开(公告)号：US4635220A
公开(公告)日：1987-01-06
申请号：US549809
申请日：1983-11-08
申请人： Hideaki Yabe , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki , Masaharu Fukuta
发明人： Hideaki Yabe , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki , Masaharu Fukuta
CPC分类号： G06F7/4917
摘要： A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.
摘要翻译： 二进制编码十进制数分割装置，其中以二进制编码十进制表示的商以逐个数字为基础通过使用商预测表和一组多值寄存器来确定，并且其中从 商预测表在预测商正确的情况下完整使用，否则预测商减1，其中存储在商预测表中的值与冗余位一起预先修改为（0110）2至（1111）2 二进制编码十进制表示。 通过使用修改的预测商的四位中的三位来选择多值寄存器，而在商确定时，从商预测表的输出值中减去用于修改的值，从而导出一个预测商的预测商 数字。 利用这种布置，从商预测表读出的一位数的预测商的四位中的三位可以直接用作选择相关除数多寄存器的选择信号。
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公开(公告)号：US4677583A
公开(公告)日：1987-06-30
申请号：US625131
申请日：1984-06-27
申请人： Toru Ohtsuki , Yoshio Oshima , Sako Ishikawa , Hideaki Yabe , Masaharu Fukuta
发明人： Toru Ohtsuki , Yoshio Oshima , Sako Ishikawa , Hideaki Yabe , Masaharu Fukuta
CPC分类号： G06F7/4915
摘要： An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.
摘要翻译： 用于十进制乘法的装置将二进制编码十进制（BCD）的乘法器分成多个组，生成多个部分乘积乘以BCD的被乘数和连续循环的多组乘法器，并将它们添加到中间乘积 先前产生的部分产品的总和。 部分乘积和中间乘积的加法由进位保存加法器进行。 在第一个循环中，将中间产品设置为零，并且将中间产品和部分产品中的任一个的每个数字加到6上，并且部分产品和中间产品的添加由 连续循环中的进位保存加法器循环。 在最后一个循环中，进位保存加法器的和和进位由全加器相加，根据全加器各位的进位转移的存在，对每个数位进行6减，结果值为 输出为乘法结果。
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