-
公开(公告)号：US5515520A
公开(公告)日：1996-05-07
申请号：US337411
申请日：1994-11-07
Applicant: Koichi Hatta , Koichi Kuroiwa
Inventor： Koichi Hatta , Koichi Kuroiwa
CPC classification number: G06F7/483 , G06F9/3877 , G06F2207/382
Abstract: A data processing system includes a single-precision operation unit, a double-precision operation unit, a single-precision data to double-precision data conversion unit, and a double-precision data to single-precision data conversion unit. When two single-precision operations are simultaneously carried out, the single-precision operation unit performs a single-precision operation upon a group of single-precision data, and the double-precision operation unit with the single-precision data to double-precision data conversion unit and the double-precision data to single-precision data conversion unit perform a single-precision operation upon the other group of single-precision data. When a double-precision operation is carried out, the double-precision operation unit performs a double-precision operation upon a group of double-precision data.
Abstract translation: 数据处理系统包括单精度运算单元，双精度运算单元，单精度数据双精度数据转换单元，双精度数据单精度数据转换单元。 当同时执行两个单精度操作时，单精度运算单元对一组单精度数据执行单精度运算，双精度运算单元将单精度数据转换为双精度数据 转换单元和双精度数据到单精度数据转换单元对另一组单精度数据执行单精度运算。 当进行双精度运算时，双精度运算部对一组双精度数据进行双精度运算。
-
公开(公告)号：US5034912A
公开(公告)日：1991-07-23
申请号：US462379
申请日：1990-01-09
Applicant: Sumitaka Takeuchi , Hiroyuki Kouno
Inventor： Sumitaka Takeuchi , Hiroyuki Kouno
Abstract: A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation. The circuit for generating the signal indicative of the result of multiplication includes a circuit for logically processing, by logic gates, the control signal and the digital multiplicand. The logic gate circuit includes a circuit for detecting coincidence/non-coincidence between a pattern of the generated control signal and a bit pattern of the digital multiplicand, and a circuit responsive to the output of the detecting circuit for activating one of a plurality of possible signals indicating the results of multiplication.
Abstract translation: 不需要数模转换器的乘法处理电路包括用于将数字乘法系数乘以数字乘法器并输出乘法结果作为模拟电流信号的电路。 乘法处理电路包括用于解码数字乘法系数以产生一个或多个控制信号的电路，响应于数字被乘数的电路和产生的控制信号，用于产生以十进制格式表示乘法结果的信号 数字乘法器的数字乘法系数，以及用于将表示乘法结果的信号转换成相应幅度的模拟电流信号的电路。 每个控制信号以十进制形式表示至少一个数字乘法系数。 用于产生指示乘法结果的信号的电路包括逻辑门逻辑处理控制信号和数字被乘数的电路。 逻辑门电路包括用于检测所产生的控制信号的模式与数字被乘数的位模式之间的符合/非重合的电路，以及响应于检测电路的输出的电路，用于激活多个可能的 指示乘法结果的信号。
-
公开(公告)号：US4866651A
公开(公告)日：1989-09-12
申请号：US89649
申请日：1987-08-26
Applicant: J. Hartmut Bleher , Axel T. Gerlicher , Siegfried M. Rump , Dieter K. Unkauf
Inventor： J. Hartmut Bleher , Axel T. Gerlicher , Siegfried M. Rump , Dieter K. Unkauf
CPC classification number: G06F7/485
Abstract: For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.
Abstract translation: 为了连续地添加一系列浮点数，使用浮点加法器级（图2），除了两个浮点操作数的和之外，它还将从较小的操作数中截取的余数作为浮点数 。 为了获得操作数的精确总和，这些余数以中间和的形式相加。 用于并联操作的电路装置包括串联连接的浮点加法器级（图6），中间和出现在每级的输出端，中间余数被缓冲。 在每种情况下，剩余物都传递到下一个阶段，它们的值减少直到它们为零。 串行操作装置（图8）包括用于缓冲中间和和最终结果的单个加法器级（30）和寄存器堆栈（34）。 发生的余数存储在加法器级的输出端的余数寄存器（32）中，并加到中间和直到余数为零。 随后，将新的操作数应用于加法器级的输入。
-
公开(公告)号：US4546447A
公开(公告)日：1985-10-08
申请号：US459149
申请日：1983-01-19
Applicant: Hideo Sawada
Inventor： Hideo Sawada
CPC classification number: G06F7/535 , G06F7/4917
Abstract: A division apparatus. A quotient of one digit and a remainder are determined by repeating execution of a single type processing of adding an integral multiple of a divisor and an intermediate remainder. The apparatus includes first, second and third registers for storing a dividend or the intermediate remainder, the integral multiple of a divisor and a carry resulted from a preceding operation, respectively, a selection circuit for selecting the complement of the integral multiple of the divisor when the carry is zero while selecting the integral multiple of the divisor when the carry is 0, an arithmetic circuit for performing adding operation on the output of the selection circuit and the content of the first register with the carry being served as the initial carry, and a counter for counting a number which corresponds to the integral multiple of the divisor. The result of the arithmetic operation which is executed in dependence on the value assumed by the carry is placed in the first register. The quotient is determined on the basis of the content of the counter.
Abstract translation: 分割装置。 通过重复执行添加除数和中间余数的整数倍的单一类型处理来确定一位数和余数的商。 该装置包括用于分别存储除数或中间余数的第一，第二和第三寄存器，分别由先前操作产生的除数的整数倍和进位，用于选择除数积分倍数的补数的选择电路， 当进位为0时选择除数的整数倍时，进位为零，用于对选择电路的输出执行加法运算的运算电路和作为初始进位的进位的第一寄存器的内容，以及 用于对与除数的整数倍相对应的数字进行计数的计数器。 根据进位所假设的值执行的算术运算结果位于第一个寄存器中。 商根据计数器的内容确定。
-
公开(公告)号：US4456955A
公开(公告)日：1984-06-26
申请号：US294053
申请日：1981-08-18
Applicant: Tomoatsu Yanagita , Motonobu Nagafuji
Inventor： Tomoatsu Yanagita , Motonobu Nagafuji
IPC: G06F7/38 , G06F7/00 , G06F7/48 , G06F7/493 , G06F7/50 , G06F7/506 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/34 , G06F13/00
CPC classification number: G06F9/3001 , G06F7/48 , G06F7/49936
Abstract: A data processing system has an arithmetic operating unit to process a plurality of bytes at a time and carries out an arithmetic operation on first and second operands each starting from any desired address on a main memory and having any desired number of byte length. The second operand is aligned to an operand position of the first operand and the aligned second operand is supplied to the operating unit while the first operand is supplied as it is to the operating unit. Since the second operand is aligned to the operand position of the first operand before it is processed in the operating unit, the number of times of alignment is reduced.
Abstract translation: 数据处理系统具有算术运算单元，用于一次处理多个字节，并对从主存储器上的任何所需地址开始并且具有任何期望数量的字节长度的第一和第二操作数执行算术运算。 第二操作数与第一操作数的操作数位置对齐，并且将对准的第二操作数提供给操作单元，同时将第一操作数原样提供给操作单元。 由于第二操作数在操作单元处理之前与第一操作数的操作数位置对齐，因此减少对准次数。
-
Patent Agency Ranking
公开(公告)号：US4409668A
公开(公告)日：1983-10-11
申请号：US242142
申请日：1981-03-09
Applicant: Junichi Yoshida
Inventor： Junichi Yoshida
CPC classification number: G06F3/1407
Abstract: A round-off type of numeric data display apparatus which has at least X, Y, Z and K registers, and which stores in said X register a previous data item obtained by a previous one of arithmetic operations convergently producing a result in turn, stores in said Y register an immediately succeeding data item obtained by an immediately succeeding one to said previous one of said arithmetic operations, stores in said K register that number of digit-place data items to be rounded-off of said immediately succeeding data item which has been obtained by the arithmetic operation in an arithmetic-operational section connected to said X, Y, Z and K registers, subjects said immediately succeeding data item to rounding-off operation in said arithmetic-operational section on the basis of the contents item of said K register and stores the result of said rounding-off operation in said Z register, transfers the contents item of said Z register and a decimal point code of said Y register to a display buffer connected to said Y and Z registers, and displays only numeric data of reliable digit-place number from a display section connected to said display buffer.
Abstract translation: 具有至少X，Y，Z和K寄存器的四舍五入的数字数据显示装置，并且在所述X寄存器中存储由前一个算术运算获得的先前数据项，依次收敛产生结果，存储 在所述Y寄存器中，通过紧随其后的一个到所述前一个所述算术运算获得的紧随其后的数据项在所述K个寄存器中存储所述紧随其后的数据项的四舍五入的数位数据项的数目， 通过在与所述X，Y，Z和K寄存器连接的算术运算部分中的算术运算来获得，所述算术运算部分将所述紧接着的数据项目的对象基于所述算术运算部分的内容项目进行舍入运算， K寄存器并将所述舍入运算的结果存储在所述Z寄存器中，将所述Z寄存器的内容项和所述Y寄存器的小数点代码传送到显示器bu 连接到所述Y和Z寄存器，并且仅从连接到所述显示缓冲器的显示部分仅显示可靠的数字位数的数字数据。
-
公开(公告)号：US4118786A
公开(公告)日：1978-10-03
申请号：US758378
申请日：1977-01-10
Applicant: Samuel R. Levine , Shanker Singh , Arnold Weinberger
Inventor： Samuel R. Levine , Shanker Singh , Arnold Weinberger
CPC classification number: G06F7/494 , G06F7/508 , G06F2207/3844 , G06F2207/4921
Abstract: An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.
Abstract translation: 一个改进的系统，将两个数字加在一起。 数字可以以二进制形式或二进制编码十进制形式表示（其中每个十进制数字由其等效的四个二进制位表示）。 通过利用“无关”十进制输入条件，可以获得可以对两种类型的数字进行操作的进位预读加法器的最小实现。
-
公开(公告)号：US5170371A
公开(公告)日：1992-12-08
申请号：US175968
申请日：1988-03-31
Applicant: Henry M. Darley
Inventor： Henry M. Darley
CPC classification number: G06F7/4876 , G06F7/49936 , G06F7/49947
Abstract: A rounding circuit (10) for converting and rounding an M bit output from an adder array (12) into a N bit binary magnitude representation includes an incrementer (18) which increments the output of the adder array (12) prior to conversion. A borrow calculator (16) generates a select signal to a multiplexer indicating whether covnersion of the M bit number requires a borrow from the upper N bits. The select signal is used to choose between the incremented or non-incremented output. A converter/decrementer (22) converts the selected output of the multiplexer (20) into a binary magnitude number and also computes the magnitude representation decremented by one. A rounding circuitry (24) computes the rounding direction based on a control signal from control circuitry (26). The rounder circuit (10) calculates rounding information for two cases: (a) assuming that no normalization of the converted value is necessary and (b) assuming that normalization of the converted value is necessary. A selector/shifter (28) chooses between the decremented and non-decremented values based on the rounding information.
Abstract translation: 用于将从加法器阵列（12）输出的M位转换和舍入为N位二进制幅度表示的舍入电路（10）包括在转换之前增加加法器阵列（12）的输出的递增器（18）。 借用计算器（16）向多路复用器产生选择信号，指示M比特数的累加是否需要来自高N比特的借位。 选择信号用于在递增或非递增输出之间进行选择。 A转换器/减法器（22）将多路复用器（20）的所选输出转换为二进制数量，并且还计算减1的幅度表示。 舍入电路（24）基于来自控制电路（26）的控制信号来计算舍入方向。 圆形电路（10）计算两种情况的舍入信息：（a）假设不需要转换值的归一化，（b）假设转换值的归一化是必要的。 选择器/移位器（28）基于舍入信息在递减值和非递减值之间进行选择。
-
公开(公告)号：US4734878A
公开(公告)日：1988-03-29
申请号：US794094
申请日：1985-10-31
Applicant: Patrick L. Sutcliffe
Inventor： Patrick L. Sutcliffe
CPC classification number: G06F7/5525
Abstract: Circuitry for computing the square root of a number wherein the input number is partitioned into digit pairs left and right of the radix point. Pairs of zeros are added after the radix point for each digit of the desired precision. The most significant zero digit pairs are skipped to the first digit pair which is not zero, accordingly the first answer bit is a 1. A residue is formed by subtracting the 1 from the digit pair, multiplying by 4, and adding the next most significant digit pair. The procedure is repeated for subsequent bit pairs by defining trial divisors and determining residue values.
Abstract translation: 用于计算数字的平方根的电路，其中输入数被分成小数点左右的数字对。 在所需精度的每个数字的小数点之后添加零对。 最重要的零位对被跳过到不为零的第一数字对，因此第一个应答位为1.通过从数字对中减去1乘以4并将下一个最高有效值 数字对。 通过定义试验因子和确定残差值，对后续位对重复该过程。
-
公开(公告)号：US4724529A
公开(公告)日：1988-02-09
申请号：US701556
申请日：1985-02-14
Applicant: Suren Irukulla , Bimal V. Patel
Inventor： Suren Irukulla , Bimal V. Patel
CPC classification number: G06F7/535 , G06F7/49 , G06F7/4917 , G06F7/5375
Abstract: A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.
Abstract translation: 基数β恢复分裂的方法和装置。 分割过程分四个阶段进行。 在第一阶段中，输入操作数被变换以产生位于指定数值范围内的除数。 接下来，过渡阶段涉及从转换的分子生成初始的基数β商数。 该过程的迭代阶段根据递归方法产生连续的部分余数。 从符号和每个这些部分余数的单个基数β数字，该过程生成基数β商数。 此外，可以与过渡和迭代阶段同时运行的第四阶段涉及累积连续生成的商数以产生最终商值。
-
-
-
-
-
-
-
-
-
Search Results
45
records
(took 0.014 seconds)
