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    Circuit arrangement for generating a reference current and oscillator circuit having the circuit arrangement
    11.
    发明授权
    Circuit arrangement for generating a reference current and oscillator circuit having the circuit arrangement 有权
    用于产生具有电路装置的参考电流和振荡器电路的电路装置

    公开(公告)号：US07098752B2

    公开(公告)日：2006-08-29

    申请号：US10931173

    申请日：2004-08-31

    Applicant: Jürgen Oehm

    Inventor： Jürgen Oehm

    IPC: H03B5/10 ,  H03J7/04 ,  H03L7/099

    CPC classification number: H03B5/1271 ,  H03B5/129 ,  H03B2201/0283

    Abstract: A circuit arrangement for generating a reference current and also an oscillator circuit having the circuit arrangement are disclosed the arrangement includes a capacitance connected to an input of a voltage-controlled current source. Two amplifiers having different drive capabilities, between which a switching can be effected, are provided to drive the capacitance. An LC oscillator can be fed with the reference current in a current-controlled manner and at the same time in a particularly low-noise manner.

    Abstract translation: 公开了一种用于产生参考电流的电路装置以及具有电路装置的振荡器电路，该装置包括连接到电压控制电流源的输入的电容。 提供具有不同驱动能力的两个放大器，其间可进行切换以驱动电容。 可以以电流控制的方式和同时以特别低噪声的方式将LC振荡器馈送到参考电流。

    Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors
    12.
    发明授权
    Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors 有权
    使用mos场效应晶体管数字控制集成电路器件的电容的方法和装置

    公开(公告)号：US06211745B1

    公开(公告)日：2001-04-03

    申请号：US09304443

    申请日：1999-05-03

    Applicant: Lars Henrik Mucke ,  Christopher Dennis Hull ,  Lars Gustaf Jansson

    Inventor： Lars Henrik Mucke ,  Christopher Dennis Hull ,  Lars Gustaf Jansson

    IPC: H01L2993

    CPC classification number: H03F3/45085 ,  H01L27/0805 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03F1/56 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

    Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented.

    Abstract translation: 一种使用MOS-FET器件数字控制集成电路器件的电容的方法和装置。 根据本发明的一个方面，提出了一种一位或“二进制”变容二极管，其中MOS-FET器件的栅极 - 体积电容表现出对其栅极和阱注入区域之间施加的直流电压的依赖性。 二元电容器的电容电压特性具有三个主要区域：（1）具有很小或没有电压依赖性并具有等于C1的第一低电容的电容的第一相对平坦的区域; （2）存在电压依赖性的倾斜区域; 和（3）几乎没有或没有电压依赖性并且电容等于C2的第二较高电容的第二相对平坦的区域。 通过将所施加的直流电压的极性从正值改变为负值，可以将二进制电容器的电容从C1改变为C2。 多个二进制电容器被配置成并联布置以产生数字控制的电容器。 数字控制电容器可用于需要严格控制的调谐网络的任何集成电路中。 一种应用是压控振荡器（VCO），其中VCO的中心输出频率通过数字修改VCO的数字控制电容器的电容来校准。 提出了一种用于确定VCO是否需要校准的装置，以及用于校准VCO的中心输出频率的装置。

    High frequency clock generator with multiplexer
    14.
    发明授权
    High frequency clock generator with multiplexer 失效
    高频时钟发生器与多路复用器

    公开(公告)号：US5414308A

    公开(公告)日：1995-05-09

    申请号：US921889

    申请日：1992-07-29

    Applicant: I-Shi Lee ,  Tim H. T. Shen ,  Stephen R. M. Huang ,  Judy C. L. Kuo

    Inventor： I-Shi Lee ,  Tim H. T. Shen ,  Stephen R. M. Huang ,  Judy C. L. Kuo

    IPC: H03B1/00 ,  H03B1/04 ,  H03B5/32 ,  H03L7/00

    CPC classification number: H03B1/04 ,  H03B2201/0283 ,  H03B5/32

    Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.

    Abstract translation: 高频时钟发生器具有能够提供耦合到多个振荡器电路的各种输出频率的多个石英晶体。 来自每个振荡器电路的输出线耦合到一个或多个复用器，使得用户可以同时选择一个或多个输出频率。 多个时钟振荡器电路和多路复用器被制造为集成电路，以最小化天气和灰尘的劣化影响，提供固定的电容值和逆变器带宽乘积，并改善时钟发生器的稳定性。

    OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT
    17.
    发明申请
    OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT 有权
    振荡器，电子设备和移动对象

    公开(公告)号：US20160226447A1

    公开(公告)日：2016-08-04

    申请号：US15014283

    申请日：2016-02-03

    Applicant: Seiko Epson Corporation

    Inventor： Akihiro FUKUZAWA

    IPC: H03B5/32

    CPC classification number: H03B5/32 ,  H03B5/129 ,  H03B2200/0062 ,  H03B2201/0283 ,  H03B2201/038 ,  H03B2202/06

    Abstract: An oscillator includes an input terminal, an oscillation circuit section configured to cause a resonator to resonate to output an oscillator signal, a digital input section to which a signal for controlling an oscillation frequency of the oscillation circuit section is input via the input terminal, and a first bias circuit section including a constant current source configured to supply a reference current to the digital input section.

    Abstract translation: 振荡器包括输入端子，被配置为使谐振器谐振以输出振荡器信号的振荡电路部分，经由输入端子输入用于控制振荡电路部分的振荡频率的信号的数字输入部分;以及 第一偏置电路部分，包括被配置为向数字输入部分提供参考电流的恒流源。

    Split varactor array with improved matching and varactor switching scheme
    18.
    发明授权
    Split varactor array with improved matching and varactor switching scheme 有权
    具有改进的匹配和变容二极管切换方案的分裂变容二极管阵列

    公开(公告)号：US08779867B2

    公开(公告)日：2014-07-15

    申请号：US13281871

    申请日：2011-10-26

    Applicant: Edwin Thaller ,  Roberto Nonis

    Inventor： Edwin Thaller ,  Roberto Nonis

    IPC: H03B5/12

    CPC classification number: H03B5/124 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/0208 ,  H03B2201/0283 ,  H03J2200/10

    Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

    Abstract translation: 本发明的一个实施例涉及数字控制振荡器。 振荡器包括振荡电路，变容二极管阵列和控制电路。 振荡器电路接收控制字和信号，并从控制字选择的频率的信号产生振荡器时钟信号。 变容二极管阵列具有具有增量电容值的变容二极管单元的第一阵列和具有相等电容值的变容二极管单元的第二阵列。 拆分变容二极管阵列提供电容值。 控制电路耦合到振荡器电路，并根据控制字控制分离变容二极管阵列。 控制电路设置分离变容二极管阵列的变容二极管电池。

    Method, system and apparatus for reducing oscillator frequency spiking during oscillator frequency adjustment
    19.
    发明授权
    Method, system and apparatus for reducing oscillator frequency spiking during oscillator frequency adjustment 有权
    在振荡器频率调整期间减少振荡器频率尖峰的方法，系统和装置

    公开(公告)号：US07432773B2

    公开(公告)日：2008-10-07

    申请号：US11531004

    申请日：2006-09-12

    Applicant: Vanitha Kuppusamy ,  Clark Rogers

    Inventor： Vanitha Kuppusamy ,  Clark Rogers

    IPC: H03L7/099

    CPC classification number: H03M1/0872 ,  H03B2200/0034 ,  H03B2200/0048 ,  H03B2201/0283 ,  H03L1/00 ,  H03M1/742

    Abstract: Current sources are selectively coupled to a current controlled frequency determining circuit of an oscillator. A buffer amplifier has an input coupled to the current controlled frequency determining circuit of the oscillator and the buffer amplifier output is selectively coupled to the current sources not coupled to the frequency determining circuit of the oscillator. The buffer amplifier output maintains substantially the voltage of the current controlled frequency determining circuit on each of the current sources not coupled to the frequency determining circuit so that when any current source is coupled thereto, there is substantially no voltage difference therebetween. This substantially prevents generation of undesirable frequency spikes during coupling of the current sources to the frequency determining circuit of the oscillator.

    Abstract translation: 电流源选择性地耦合到振荡器的电流控制频率确定电路。 缓冲放大器具有耦合到振荡器的电流控制频率确定电路的输入，并且缓冲放大器输出选择性地耦合到未耦合到振荡器的频率确定电路的电流源。 缓冲放大器输出基本上维持不耦合到频率确定电路的每个电流源上的电流控制频率确定电路的电压，使得当任何电流源耦合到其上时，它们之间基本上没有电压差。 这实质上防止了在将电流源耦合到振荡器的频率确定电路期间产生不期望的频率尖峰。

    Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device
    20.
    发明申请
    Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device 有权

    公开(公告)号：US20010020875A1

    公开(公告)日：2001-09-13

    申请号：US09824277

    申请日：2001-04-02

    Applicant: Silicon Wave, Inc.

    Inventor： Lars Gustaf Jansson

    IPC: H03B005/12 ,  H03L007/099

    CPC classification number: H03F3/45085 ,  H01L27/0805 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03F1/56 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

    Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or nullbinarynull varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented.

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