公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F13/12 ,  G06F12/02

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20090283600A1

公开(公告)日：2009-11-19

申请号：US12285187

申请日：2008-09-30

Applicant: Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

Inventor： Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

IPC: G06K7/06

CPC classification number: G06F13/385 ,  G06F13/4072

Abstract: A card reader includes a card interface, and one of the pins of the card interface is selected to decide the state of the card interface. The card reader further includes a control circuit to detect the logic state of the selected pin. If the logic state is a first one, the control circuit decides the card interface is enabled; otherwise, if the logic state is a second one, the control circuit decides the card interface is disabled. In some embodiments, a switch is connected between the selected pin and a power supply or a ground terminal, to be switched by a control signal to enable or disable the card interface.

Abstract translation: 读卡器包括卡接口，并且选择卡接口的一个引脚来决定卡接口的状态。 读卡器还包括用于检测所选引脚的逻辑状态的控制电路。 如果逻辑状态是第一个，控制电路决定卡接口被使能; 否则，如果逻辑状态是第二个逻辑状态，则控制电路决定卡接口被禁用。 在一些实施例中，开关连接在所选择的引脚和电源或接地端子之间，以通过控制信号切换以启用或禁用卡接口。