公开(公告)号：US11423952B2

公开(公告)日：2022-08-23

申请号：US16715249

申请日：2019-12-16

Applicant: XILINX, INC.

Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

IPC: G11C5/14 ,  H01L25/18 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094

Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

公开(公告)号：US20210183412A1

公开(公告)日：2021-06-17

申请号：US16715249

申请日：2019-12-16

Applicant: XILINX, INC.

Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

IPC: G11C5/14 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0185 ,  H01L25/18

Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

公开(公告)号：US10411710B1

公开(公告)日：2019-09-10

申请号：US16211149

申请日：2018-12-05

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Sree RKC Saraswatula ,  Jing Jing Chen ,  Teja Masina ,  Narendra Kumar Pulipati ,  Santosh Yachareni

IPC: H03K19/177

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

公开(公告)号：US10396799B1

公开(公告)日：2019-08-27

申请号：US15839462

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Vishwak R Manda ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou ,  Jing Jing Chen ,  Michael Tsivyan

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/0185

Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.

公开(公告)号：US09721649B1

公开(公告)日：2017-08-01

申请号：US15237395

申请日：2016-08-15

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Jing Jing Chen

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/04

Abstract: A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described.

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。