-
公开(公告)号：US10296673B1
公开(公告)日：2019-05-21
申请号：US14723188
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Ishita Ghosh , Hem C. Neema , Jason Villarreal , Saikat Bandyopadhyay , Kumar Deepak
IPC: G06F17/50
Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.
-
12.发明授权公开(公告)号：US09223910B1
公开(公告)日：2015-12-29
申请号：US14159855
申请日：2014-01-21
Applicant: Xilinx, Inc.
Inventor： Ishita Ghosh , Saikat Bandyopadhyay , Kumar Deepak , Hem C. Neema , David K. Liddell
IPC: G06F17/50
CPC classification number: G06F17/5022
Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.
Abstract translation: 公开了一种用于编译用于模拟电路设计的HDL规范的方法。 电路设计由HDL规范进行阐述，内存位置分配给精密电路设计的正式和实际。 对于具有兼容的形式和实际的每个端口，存储器位置的分配设置用于形式的参考指针和用于实际引用相同存储器位置的引用指针。 对于具有不兼容的形式和实际的每个端口，存储器位置的分配设置形式的参考指针和用于实际引用的参考指针以引用不同的相应存储器位置。 生成针对详细电路设计的仿真代码建模，其将使用单个写入操作兼容的端口的正式和实际更新到引用的存储器位置。
-
公开(公告)号：US20250156617A1
公开(公告)日：2025-05-15
申请号：US18509189
申请日：2023-11-14
Applicant: Xilinx, Inc.
Inventor： Lin-Ya Yu , Alexandre Isoard , Hem C. Neema , Luciano Lavagno , Chen Qianqiao , Xu Yang
IPC: G06F30/3312 , G06F119/12
Abstract: Computer-based co-simulation includes simulating a circuit design and a co-simulation model configured to model circuitry that operates in coordination with a hardware implementation of the circuit design. In response to a request for a data transfer received by the co-simulation model from the circuit design, a ready signal is provided from the co-simulation model to the circuit design after a first predetermined number of simulation clock cycles corresponding to an initiation interval of the circuitry modeled by the co-simulation model. In response to receiving state information for the data transfer, a response from the co-simulation model is provided to the circuit design after a second predetermined number of simulation clock cycles corresponding to a response time of the circuitry modeled by the co-simulation model.
-
14.发明授权公开(公告)号：US10802995B2
公开(公告)日：2020-10-13
申请号：US16046602
申请日：2018-07-26
Applicant: Xilinx, Inc.
Inventor： Sarabjeet Singh , Hem C. Neema , Sonal Santan , Khang K. Dao , Kyle Corbett , Yi Wang , Christopher J. Case
IPC: G06F9/38 , G06F13/16 , G06F9/46 , G06F12/0873 , G06F12/1045 , G06F12/1081
Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.
-
15.发明申请公开(公告)号：US20200081850A1
公开(公告)日：2020-03-12
申请号：US16046602
申请日：2018-07-26
Applicant: Xilinx, Inc.
Inventor： Sarabjeet Singh , Hem C. Neema , Sonal Santan , Khang K. Dao , Kyle Corbett , Yi Wang , Christopher J. Case
IPC: G06F13/16 , G06F12/1045 , G06F12/0873 , G06F12/1081 , G06F9/46
Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.
-
Patent Agency Ranking
公开(公告)号：US20240411967A1
公开(公告)日：2024-12-12
申请号：US18333372
申请日：2023-06-12
Applicant: Xilinx, Inc.
Inventor： Lin-Ya Yu , Alexandre Isoard , Hem C. Neema
IPC: G06F30/323
Abstract: High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.
-
公开(公告)号：US11836426B1
公开(公告)日：2023-12-05
申请号：US17819884
申请日：2022-08-15
Applicant: Xilinx, Inc.
Inventor： Fangqing Du , Alexandre Isoard , Lin-Ya Yu , Hem C. Neema
IPC: G06F30/327 , G06F15/80
CPC classification number: G06F30/327 , G06F15/80
Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.
-
18.发明公开公开(公告)号：US20230305949A1
公开(公告)日：2023-09-28
申请号：US17656236
申请日：2022-03-24
Applicant: Xilinx, Inc.
Inventor： Lin-Ya Yu , Alexandre Isoard , Hem C. Neema
CPC classification number: G06F11/3688 , G06F8/311
Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.
-
19.发明授权公开(公告)号：US11762762B1
公开(公告)日：2023-09-19
申请号：US17656236
申请日：2022-03-24
Applicant: Xilinx, Inc.
Inventor： Lin-Ya Yu , Alexandre Isoard , Hem C. Neema
CPC classification number: G06F11/3688 , G06F8/311
Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.
-
公开(公告)号：US11720422B1
公开(公告)日：2023-08-08
申请号：US17198887
申请日：2021-03-11
Applicant: Xilinx, Inc.
Inventor： Hem C. Neema , Sonal Santan , Soren T. Soe , Stephen P. Rozum , Nik Cimino
CPC classification number: G06F9/545 , G06F8/44 , G06F21/53 , G06F21/572 , G06F8/65
Abstract: A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.014 seconds)
