公开(公告)号：US11520570B1

公开(公告)日：2022-12-06

申请号：US17344472

申请日：2021-06-10

Applicant: Xilinx, Inc.

Inventor： Dan Liu ,  Gai Liu ,  Luciano Lavagno

IPC: G06F9/45 ,  G06F8/41 ,  G06F8/20

Abstract: Controlling execution of application-specific hardware pipelines includes detecting, using computer hardware, a loop construct contained in a function within a design specified in a high-level programming language, extracting, using the computer hardware, the loop construct from the function into a newly generated function of the design, and generating, using the computer hardware, a state transition graph corresponding to the loop construct. The state transition graph can be pruned by relocating operations from the function entry state and the function exit state into the loop region. A circuit design defining, at least in part, a pipeline hardware architecture implementing the loop construct can be generated using the computer hardware based, at least in part, on the pruned state transition graph.

公开(公告)号：US20250156617A1

公开(公告)日：2025-05-15

申请号：US18509189

申请日：2023-11-14

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema ,  Luciano Lavagno ,  Chen Qianqiao ,  Xu Yang

IPC: G06F30/3312 ,  G06F119/12

Abstract: Computer-based co-simulation includes simulating a circuit design and a co-simulation model configured to model circuitry that operates in coordination with a hardware implementation of the circuit design. In response to a request for a data transfer received by the co-simulation model from the circuit design, a ready signal is provided from the co-simulation model to the circuit design after a first predetermined number of simulation clock cycles corresponding to an initiation interval of the circuitry modeled by the co-simulation model. In response to receiving state information for the data transfer, a response from the co-simulation model is provided to the circuit design after a second predetermined number of simulation clock cycles corresponding to a response time of the circuitry modeled by the co-simulation model.

公开(公告)号：US20230032302A1

公开(公告)日：2023-02-02

申请号：US17385261

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Luciano Lavagno ,  Xin Jin ,  Dan Liu ,  Thomas Bollaert ,  Hem C. Neema ,  Chaosheng Shi

IPC: G06F9/52 ,  G06F30/20 ,  G06F5/06

Abstract: Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.