公开(公告)号：US6097651A

公开(公告)日：2000-08-01

申请号：US345971

申请日：1999-06-30

申请人： Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

发明人： Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C7/1045 ,  G11C7/12

摘要： A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

摘要翻译： 随机存取存储器（RAM）装置包括存储器单元中的缓冲器，以将锁存电路与读位线隔离。 因此，避免了由读取位线上的电容性负载引起的读取干扰错误。 此外，对于写位线的预充电要求被简化，因为缓冲器允许存储单元中的锁存电路的优化。 RAM装置包括在执行写入操作之前将写入位线预充电到接地参考电压的预充电电路。 通过将写位线预充电到接地参考电压，避免了由写位线上的电容负载引起的写干扰问题。 此外，通过将写入位线耦合到接地参考电压，通过对写入位线进行预充电，很少或没有电力消耗。