公开(公告)号：US20200295084A1

公开(公告)日：2020-09-17

申请号：US16887193

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L27/11507 ,  H01L45/00 ,  H01L43/12 ,  H01L27/22

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

公开(公告)号：US20200098828A1

公开(公告)日：2020-03-26

申请号：US16695537

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L23/522

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.

公开(公告)号：US20200091425A1

公开(公告)日：2020-03-19

申请号：US16693946

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

公开(公告)号：US20200058858A1

公开(公告)日：2020-02-20

申请号：US16662422

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

公开(公告)号：US10566387B2

公开(公告)日：2020-02-18

申请号：US16108594

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/102

Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.

公开(公告)号：US20190386204A1

公开(公告)日：2019-12-19

申请号：US16552169

申请日：2019-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20190355788A1

公开(公告)日：2019-11-21

申请号：US16156026

申请日：2018-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L45/00

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

公开(公告)号：US10276485B2

公开(公告)日：2019-04-30

申请号：US15715487

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L23/498 ,  H01L23/532 ,  H01L23/49

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.

公开(公告)号：US20190123271A1

公开(公告)日：2019-04-25

申请号：US16227096

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Sheng-Hung Shih ,  Wen-Chun You

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.

公开(公告)号：US20190067373A1

公开(公告)日：2019-02-28

申请号：US15904963

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L45/00

Abstract: In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.