公开(公告)号：US20170207387A1

公开(公告)日：2017-07-20

申请号：US15403399

申请日：2017-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Sheng Yang ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Manish Kumar Singh

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/122 ,  H01L45/146 ,  H01L45/1666 ,  H01L45/1691

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.