公开(公告)号：US20210104598A1

公开(公告)日：2021-04-08

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US09178080B2

公开(公告)日：2015-11-03

申请号：US13685029

申请日：2012-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alex Kalnitsky ,  Felix Ying-Kit Tsui ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Jyun-Ying Lin

IPC: H01L29/94 ,  H01L49/02

CPC classification number: H01L29/945 ,  H01L28/91

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及高密度电容器结构。 一些实施例包括具有形成在其中的多个沟槽的导电区域的半导体衬底。 第一电介质层形成在相应的底部和相应的沟槽的各个侧壁部分之间。 第一导电层形成在沟槽中并且在第一介电层上方，其中第一介电层用作导电区域和第一导电层之间的第一电容器电介质。 第二电介质层形成在沟槽中并在第一导电层之上。 第二导电层形成在沟槽中并在第二介电层上方，其中第二介电层用作第一导电层和第二导电层之间的第二电容器电介质。 还公开了其他实施例。

公开(公告)号：US20140145299A1

公开(公告)日：2014-05-29

申请号：US13685029

申请日：2012-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alex Kalnitsky ,  Felix Ying-Kit Tsui ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Jyun-Ying Lin

IPC: H01L49/02

CPC classification number: H01L29/945 ,  H01L28/91

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及高密度电容器结构。 一些实施例包括具有形成在其中的多个沟槽的导电区域的半导体衬底。 第一电介质层形成在相应的底部和相应的沟槽的各个侧壁部分之间。 第一导电层形成在沟槽中并且在第一介电层上方，其中第一介电层用作导电区域和第一导电层之间的第一电容器电介质。 第二电介质层形成在沟槽中并在第一导电层之上。 第二导电层形成在沟槽中并在第二介电层上方，其中第二介电层用作第一导电层和第二导电层之间的第二电容器电介质。 还公开了其他实施例。