公开(公告)号：US10665550B2

公开(公告)日：2020-05-26

申请号：US16043355

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US08966426B1

公开(公告)日：2015-02-24

申请号：US14057059

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 并且将所选择的网络中的每个第二设备分配到3D IC的多层中的相应一个中，其中先前分配给该层的第二设备的总区域最小，其中第二设备根据 排序

公开(公告)号：US08701055B1

公开(公告)日：2014-04-15

申请号：US13707714

申请日：2012-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chi-Wen Chang ,  Jui-Feng Kuan ,  Wen-Shen Chou

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.

Abstract translation: 本公开提供了一种设计集成电路的系统和方法。 选择多个设备和分配给多个设备中的每一个的属性。 然后将具有分配属性的这些多个设备组合成宏小区，由此为宏小区生成密度梯度模式。 根据多个设备的组合，为宏小区确定布局相关效应（LDE）参数，并且模拟宏小区的电气性能特性。 然后可以根据模拟电气性能特性，确定的LDE参数和生成的密度梯度图案中的一个或多个来确定宏小区内的多个设备的布局分布。 可以根据宏单元的布局分布生成集成电路的设计布局。

公开(公告)号：US12154842B2

公开(公告)日：2024-11-26

申请号：US18347013

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US20230352366A1

公开(公告)日：2023-11-02

申请号：US18347013

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang HUANG ,  Chin-chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/42 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/3672 ,  H01L2225/06541

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US11094608B2

公开(公告)日：2021-08-17

申请号：US16433967

申请日：2019-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US10943729B2

公开(公告)日：2021-03-09

申请号：US16456025

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai Chang ,  Chin-Chou Liu ,  Fong-Yuan Chang ,  Hui Yu Lee ,  Yi-Kan Cheng

IPC: H01L27/08 ,  H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US09514261B2

公开(公告)日：2016-12-06

申请号：US14609508

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from a largest device area to a smallest device area; and assigning each second device in the selected network to be fabricated in a respective tier of a plurality of tiers of a three dimensional integrated circuit (3D IC) for which a total area of second devices previously assigned to said respective tier is the smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 以及将要制造的所选择的网络中的每个第二设备分配在三维集成电路（3D IC）的多层的相应层中，其中先前分配给所述相应层的第二设备的总区域最小， 第二装置根据排序按顺序分配。

公开(公告)号：US08856701B1

公开(公告)日：2014-10-07

申请号：US13795220

申请日：2013-03-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd

Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Hui Yu Lee ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

Abstract translation: 本公开涉及一种用于生成装置库的装置和方法，以及用于与由过程设计工具（PDK）支持的设计窗口的官方工具连接的布局与示意图（LVS）和寄生提取设置文件。 设备库包括无源器件，其可以在从布局前验证到集成电路设计的布局后验证的端到端设计流程中的任何点处使用。 器件库允许用于预布局验证的单个原理图，还可以进行布局后验证，从而允许极或引脚比较，并通过从器件库直接实例化器件来防止来自被动设计元件的寄生效应的双重计数 用于验证步骤。 LVS和寄生提取图形用户界面（GUI）允许将生成的设备库并入到先前存在的PDK中，而不对PDK进行任何修改。 还公开了其它装置和方法。

公开(公告)号：US20140282308A1

公开(公告)日：2014-09-18

申请号：US13795220

申请日：2013-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Hui Yu Lee ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

Abstract translation: 本公开涉及一种用于生成装置库的装置和方法，以及用于与由过程设计工具（PDK）支持的设计窗口的官方工具连接的布局与示意图（LVS）和寄生提取设置文件。 设备库包括无源器件，其可以在从布局前验证到集成电路设计的布局后验证的端到端设计流程中的任何点处使用。 器件库允许用于预布局验证的单个原理图，还可以进行布局后验证，从而允许极或引脚比较，并通过从器件库直接实例化器件来防止来自被动设计元件的寄生效应的双重计数 用于验证步骤。 LVS和寄生提取图形用户界面（GUI）允许将生成的设备库并入到先前存在的PDK中，而不对PDK进行任何修改。 还公开了其它装置和方法。