公开(公告)号：US10923426B2

公开(公告)日：2021-02-16

申请号：US16057875

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L27/118 ,  H01L27/02 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

公开(公告)号：US10854593B2

公开(公告)日：2020-12-01

申请号：US16206746

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I Huang ,  Ting-Wei Chiang ,  Shih-Chi Fu ,  Sheng-Fang Cheng ,  Jung-Chan Yang

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  G06F30/39 ,  H01L21/8234

Abstract: A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

公开(公告)号：US20200243446A1

公开(公告)日：2020-07-30

申请号：US16846690

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/02

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.

公开(公告)号：US10163882B2

公开(公告)日：2018-12-25

申请号：US15172020

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I Huang ,  Ting-Wei Chiang ,  Shih-Chi Fu ,  Sheng-Fang Cheng ,  Jung-Chan Yang

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

公开(公告)号：US20140137062A1

公开(公告)日：2014-05-15

申请号：US13677380

申请日：2012-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ping-Hung Yuh ,  Hsin-Yun Lin ,  Cheng-I Huang ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F17/5081

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously.

Abstract translation: 本公开涉及一种用于精确RC提取的方法和装置。 模式数据库被配置为存储布局模式及其相关的3D提取参数。 模式匹配工具被配置为将设计分割成多个模式，并且搜索模式数据库中的相应模式和相关联的3D提取参数。 如果相应的图案已经存储在图案数据库中，则存储在数据库中的相关3D提取参数被分配给相应的图案，而不需要提取相应的图案。 如果相应的图案不存储在图案数据库中，则提取工具提取图案并将其相关联的3D提取参数存储在图案数据库中以供将来使用。 以这种方式，对于给定的设计或多个设计，相应的图案仅被提取一次。 此外，提取结果可以同时应用于给定设计的多次，从而加快了计算时间。 提取结果也可以同时应用于多个设计。

公开(公告)号：US20140282289A1

公开(公告)日：2014-09-18

申请号：US14210490

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Li-Chun Tien ,  Pin-Dai Sue ,  Ching Hsiang Chang ,  Wen-Hao Chen ,  Cheng-I Huang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract translation: 公开了一种确定单元布局的系统和方法。 所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。 基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。 然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。

公开(公告)号：US08732641B1

公开(公告)日：2014-05-20

申请号：US13677380

申请日：2012-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hung Yuh ,  Hsin-Yun Lin ,  Cheng-I Huang ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F17/5081

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously.

Abstract translation: 本公开涉及一种用于精确RC提取的方法和装置。 模式数据库被配置为存储布局模式及其相关的3D提取参数。 模式匹配工具被配置为将设计分割成多个模式，并且搜索模式数据库中的相应模式和相关联的3D提取参数。 如果相应的图案已经存储在图案数据库中，则存储在数据库中的相关3D提取参数被分配给相应的图案，而不需要提取相应的图案。 如果相应的图案不存储在图案数据库中，则提取工具提取图案并将其相关联的3D提取参数存储在图案数据库中以供将来使用。 以这种方式，对于给定的设计或多个设计，相应的图案仅被提取一次。 此外，提取结果可以同时应用于给定设计的多次，从而加快了计算时间。 提取结果也可以同时应用于多个设计。