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公开(公告)号：US20240036867A1
公开(公告)日：2024-02-01
申请号：US18378207
申请日：2023-10-10
发明人： Naveen BHORIA , Kai CHIRCA , Timothy D. ANDERSON , Duc BUI , Abhijeet A. CHACHAD , Son Hung TRAN
IPC分类号： G06F9/30 , G06F9/38 , G06F11/00 , G06F12/0897 , G06F12/0875 , G06F9/32 , G06F11/10 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/3802 , G06F9/30014 , G06F9/30145 , G06F9/30036 , G06F9/3867 , G06F11/00 , G06F12/0897 , G06F12/0875 , G06F9/32 , G06F9/30098 , G06F11/1048 , G06F9/383 , G06F9/30112 , G06F9/345 , G06F9/30043 , G06F9/3834 , G06F9/3877 , G06F9/30101 , G06F9/3822 , G06F11/10 , G06F2212/60 , G06F2212/452 , G06F12/0811
摘要： Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.
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公开(公告)号：US20220113966A1
公开(公告)日：2022-04-14
申请号：US17557162
申请日：2021-12-21
发明人： Timothy D. ANDERSON
IPC分类号： G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F12/0875 , G06F12/0897
摘要： Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.
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公开(公告)号：US20210294639A1
公开(公告)日：2021-09-23
申请号：US17340211
申请日：2021-06-07
发明人： Duc BUI , Timothy D. ANDERSON
摘要： Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.
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14.发明申请公开(公告)号：US20190243647A1
公开(公告)日：2019-08-08
申请号：US16384434
申请日：2019-04-15
发明人： Timothy D. ANDERSON , Joseph ZBICIAK , Kai CHIRCA
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60
摘要： Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.
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15.发明申请公开(公告)号：US20180293199A1
公开(公告)日：2018-10-11
申请号：US15903183
申请日：2018-02-23
发明人： David M. THOMPSON , Timothy D. ANDERSON , Joseph R. M. ZBICIAK , Abhijeet A. CHACHAD , Kai CHIRCA , Matthew D. PIERSON
IPC分类号： G06F13/40 , G06F13/42 , H04L12/801 , G06F13/364 , H04L12/819
CPC分类号： G06F13/404 , G06F13/364 , G06F13/42 , G06F13/4282 , H04L47/10 , H04L47/215 , H04L47/39
摘要： This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
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16.发明公开公开(公告)号：US20230350681A1
公开(公告)日：2023-11-02
申请号：US18344984
申请日：2023-06-30
发明人： Timothy D. ANDERSON , Joseph ZBICIAK , Kai CHIRCA
IPC分类号： G06F9/30 , G06F9/32 , G06F12/0897 , G06F11/10 , G06F9/345 , G06F12/0875 , G06F11/00 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30123 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3861 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F9/3822 , G06F11/10 , G06F2212/452 , G06F2212/60
摘要： Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.
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公开(公告)号：US20220365787A1
公开(公告)日：2022-11-17
申请号：US17876706
申请日：2022-07-29
摘要： A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.
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公开(公告)号：US20210247980A1
公开(公告)日：2021-08-12
申请号：US17241198
申请日：2021-04-27
发明人： Timothy D. ANDERSON , Joseph ZBICIAK , Kai CHIRCA
IPC分类号： G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345
摘要： Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.
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公开(公告)号：US20210124673A1
公开(公告)日：2021-04-29
申请号：US17079074
申请日：2020-10-23
发明人： Kai CHIRCA , Timothy D. ANDERSON
IPC分类号： G06F11/36
摘要： A method includes executing software code comprising a plurality of execute packets; responsive to an execute packet of the software code being executed by a data processor core, advancing a value of a test counter register; and responsive to the value of the test counter register being equal to a terminal value, triggering an event to be handled by the software code.
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公开(公告)号：US20200371796A1
公开(公告)日：2020-11-26
申请号：US16422795
申请日：2019-05-24
发明人： Timothy D. ANDERSON , Duc BUI
IPC分类号： G06F9/30
摘要： A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.
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