公开(公告)号：US20240313749A1

公开(公告)日：2024-09-19

申请号：US18390818

申请日：2023-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory North ,  Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: H03K5/00 ,  H03K3/037 ,  H03K5/133 ,  H03K21/10

CPC classification number: H03K5/00006 ,  H03K3/037 ,  H03K5/133 ,  H03K21/10

Abstract: Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

公开(公告)号：US11669668B2

公开(公告)日：2023-06-06

申请号：US17722445

申请日：2022-04-18

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/3323

CPC classification number: G06F30/367 ,  G06F30/33 ,  G06F30/3323

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

公开(公告)号：US11334701B2

公开(公告)日：2022-05-17

申请号：US17168230

申请日：2021-02-05

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/3323

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

公开(公告)号：US20210157967A1

公开(公告)日：2021-05-27

申请号：US17168230

申请日：2021-02-05

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/3323

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

公开(公告)号：US20170124239A1

公开(公告)日：2017-05-04

申请号：US15333457

申请日：2016-10-25

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F17/504

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.