公开(公告)号：US10249610B1

公开(公告)日：2019-04-02

申请号：US15897020

申请日：2018-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Chennimalai Appaswamy ,  James P. Di Sarro ,  Krishna Praveen Mysore Rajagopal ,  Akram A. Salman ,  Muhammad Yusuf Ali

IPC: H01L27/00 ,  H01L29/00 ,  H04L21/00 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739

Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

公开(公告)号：US10181721B2

公开(公告)日：2019-01-15

申请号：US15434280

申请日：2017-02-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xianzhi Dai ,  Farzan Farbiz ,  Muhammad Yusuf Ali

IPC: H02H9/04 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.

公开(公告)号：US09425188B2

公开(公告)日：2016-08-23

申请号：US14494316

申请日：2014-09-23

Applicant: Texas Instruments Incorporated

Inventor： Muhammad Yusuf Ali ,  Rajkumar Sankaralingam

IPC: H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0285

Abstract: An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a low power supply rail (VSS) on the semiconductor surface. A trigger circuit including at least one trigger input and at least one trigger output is coupled between VDD and VSS. An active shunt including at least a large MOSFET is coupled between VDD and VSS. The trigger output is coupled to a gate electrode of the large MOSFET, and at least one diode or diode connected transistor (blocking diode) is coupled between VDD and the trigger circuit, within the trigger circuit or between the trigger output and gate electrode.

Abstract translation: 静电放电（ESD）保护集成电路（IC）包括在半导体表面上具有半导体表面的衬底，高电源轨（VDD）和低电源轨（VSS）。 包括至少一个触发输入和至少一个触发输出的触发电路耦合在VDD和VSS之间。 在VDD和VSS之间耦合至少包括一个大型MOSFET的有源分流器。 触发输出耦合到大型MOSFET的栅电极，并且至少一个二极管或二极管连接的晶体管（阻塞二极管）耦合在VDD和触发电路之间，触发电路内或触发输出与栅电极之间。