公开(公告)号：US06815981B2

公开(公告)日：2004-11-09

申请号：US10361477

申请日：2003-02-06

Applicant: Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

Inventor： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

IPC: H03K19177

CPC classification number: H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract translation: 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US06467017B1

公开(公告)日：2002-10-15

申请号：US09124649

申请日：1998-07-29

Applicant: Tony K. Ngai ,  Rakesh H. Patel ,  Srinivas T. Reddy ,  Richard G. Cliff

Inventor： Tony K. Ngai ,  Rakesh H. Patel ,  Srinivas T. Reddy ,  Richard G. Cliff

IPC: G06F1200

CPC classification number: H03K19/1776 ,  G11C7/1075 ,  G11C2207/104 ,  H03K19/17736

Abstract: A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated programmable interconnection resources. The programmable interconnection resources are arranged so that each pair of corresponding read address and write address inputs can be connected to at least one conductor in common on the conductor bus, allowing the RAM to be configured to mimic a single-port RAM as read address signals and write address signals originating at remote components of the programmable logic device “think” they are being directed to the same address inputs.

Abstract translation: 可编程逻辑器件具有嵌入式随机存取存储器（“RAM”），其可在单端口或双端口操作中同等功能。 RAM是双端口RAM，其读地址输入和写地址输入都通过两个不同的稀疏布置的可编程互连资源连接到导体总线。 可编程互连资源被布置为使得每对相应的读取地址和写入地址输入可以在导体总线上共同连接到至少一个导体，从而允许RAM被配置为模拟单端口RAM作为读取地址信号 并且写入源自可编程逻辑器件的远程组件的地址信号“认为”它们被引导到相同的地址输入。

公开(公告)号：US06392954B2

公开(公告)日：2002-05-21

申请号：US09747191

申请日：2000-12-21

Applicant: Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

Inventor： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

IPC: G11C800

CPC classification number: G11C7/1006

Abstract: A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

Abstract translation: 提供了双端口可编程逻辑器件存储器阵列。 可选择大小的数据字可以并行写入阵列并从阵列中读取。 使用写列解码器和数据选择逻辑将数据写入阵列。 由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。 使用读列解码器和数据选择逻辑从数组中读取数据。 由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。 写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。 写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

公开(公告)号：US06335634B1

公开(公告)日：2002-01-01

申请号：US09577297

申请日：2000-05-22

Applicant: Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

Inventor： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

IPC: G06F738

CPC classification number: H03K19/17736 ,  H03K19/17792

Abstract: Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

Abstract translation: 提供了用于在可编程逻辑器件上选择性地互连逻辑的可编程互连组布置。 互连组可以被编程为在设备上的各种导体之间路由信号，并且将信号从设备上的各种逻辑区域路由到各种导体。 互连组提供路由灵活性和效率，而不需要使用过多的互连资源。

公开(公告)号：US06323677B1

公开(公告)日：2001-11-27

申请号：US09542211

申请日：2000-04-04

Applicant: Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

Inventor： Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

IPC: H03K19173

CPC classification number: H03K19/17792 ,  H03K19/17728 ,  H03K19/17732

Abstract: In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

Abstract translation: 为了便于可编程逻辑器件中的乘法性能，这些器件的各个逻辑模块被构造成使得一个逻辑模块可以执行（至少）二进制乘法的一个位置和完全二进制加法的一个位置。 这使得可以减少执行乘法所需的逻辑模块的数量。 它还减少了乘法中使用的模块间连接的数量，从而倾向于减少执行乘法所需的时间。

公开(公告)号：US06222382B1

公开(公告)日：2001-04-24

申请号：US09527903

申请日：2000-03-17

Applicant: David E. Jefferson ,  Srinivas T. Reddy

Inventor： David E. Jefferson ,  Srinivas T. Reddy

IPC: G06F738

CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

Abstract: Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

公开(公告)号：US06191998B1

公开(公告)日：2001-02-20

申请号：US09452627

申请日：1999-12-01

Applicant: Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

Inventor： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

IPC: G11C800

CPC classification number: G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005

Abstract: A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

Abstract translation: 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写操作，并且来自第二可组合单端口存储器阵列的电路是 用于执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。

公开(公告)号：US06184705B2

公开(公告)日：2001-02-06

申请号：US08982964

申请日：1997-12-02

Applicant: Richard G. Cliff ,  Srinivas T. Reddy ,  Andreas Papaliolios

Inventor： Richard G. Cliff ,  Srinivas T. Reddy ,  Andreas Papaliolios

IPC: H03K19173

CPC classification number: H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

公开(公告)号：US6107825A

公开(公告)日：2000-08-22

申请号：US87630

申请日：1998-05-29

Applicant: Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Edward Jefferson

Inventor： Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Edward Jefferson

IPC: H03K19/177

CPC classification number: H03K19/17744

Abstract: A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output ("I/O") pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.

Abstract translation: 可编程逻辑器件具有围绕其周边延伸的多个导体，用于提供控制输入/输出（“I / O”）引脚所需的至少一些信号，该引脚也设置在器件周围。 这些控制信号可以包括时钟信号，输出使能信号，时钟使能信号，清除信号等。 因此，围绕周边延伸的导体被分割成多个段，其可以彼此独立地使用或可编程地缝合在一起，因此一起使用。

公开(公告)号：US6052327A

公开(公告)日：2000-04-18

申请号：US107533

申请日：1998-06-30

Applicant: Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

Inventor： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

IPC: G11C11/41 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C7/1006

Abstract: A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

Abstract translation: 提供了双端口可编程逻辑器件存储器阵列。 可选择大小的数据字可以并行写入阵列并从阵列中读取。 使用写列解码器和数据选择逻辑将数据写入阵列。 由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。 使用读列解码器和数据选择逻辑从数组中读取数据。 由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。 写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。 写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。