公开(公告)号：US09190402B2

公开(公告)日：2015-11-17

申请号：US14245079

申请日：2014-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Hwa-Sung Rhee

IPC: H01L21/02 ,  H01L27/01 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L27/016 ,  H01L21/76879 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/10852 ,  H01L27/10858 ,  H01L27/10861 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.

Abstract translation: 半导体器件包括在衬底上的层间电介质层，层间绝缘层具有上表面，下电极从层间电介质层的上表面向下延伸到层间电介质层中，下插塞具有上表面， 第一电介质层图案在下塞子的上表面上，第一介电层图案的至少一部分直接连接到下塞子的上表面，第一介电层图案上的第一金属电极图案，第一上层 电插头与第一金属电极图形电连接，第二上插头位于下插头上，第二上插头与第一上插头间隔开。

公开(公告)号：US20140332871A1

公开(公告)日：2014-11-13

申请号：US14174705

申请日：2014-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Hwa-Sung Rhee

IPC: H01L23/525 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Abstract translation: 半导体器件包括具有晶体管区域的衬底，设置在衬底的晶体管区域上的栅极结构，覆盖栅极结构的第一层间绝缘层，设置在第一层间绝缘层上的阻挡图案，以及布置在 阻塞模式。 跳线图案包括垂直穿过第一层间绝缘层以与暴露在栅极结构两侧的基板接触的跨接触插塞，以及被配置为电连接跨接触头塞的跳线部分。

公开(公告)号：US20140167180A1

公开(公告)日：2014-06-19

申请号：US14045034

申请日：2013-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  Y10S257/90

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract translation: 提供半导体器件。 半导体器件可以包括晶体管区域和电阻器区域。 晶体管区域可以包括栅极结构。 电阻器区域可以在绝缘层上包括绝缘层和电阻器结构。 栅极结构的顶表面和电阻器结构的顶表面可以是基本上共面的。

公开(公告)号：US20140131815A1

公开(公告)日：2014-05-15

申请号：US14157914

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hee Yu ,  Bong-Seok Suh ,  Yoon-Hae Kim ,  O Sung Kwon ,  Oh-Jung Kwon

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.

Abstract translation: 提供半导体器件。 半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。