公开(公告)号：US10332831B2

公开(公告)日：2019-06-25

申请号：US15638552

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

公开(公告)号：US09972527B2

公开(公告)日：2018-05-15

申请号：US15263822

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun Kim ,  Yong-Kwan Kim ,  Se-Myeong Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim

IPC: H01L21/00 ,  H01L21/768 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  G11C11/406

CPC classification number: H01L21/7682 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10885 ,  H01L28/00

Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.

公开(公告)号：US09960039B2

公开(公告)日：2018-05-01

申请号：US15291780

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Eun-Jung Kim ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.

公开(公告)号：US20170154805A1

公开(公告)日：2017-06-01

申请号：US15263822

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-EUN KIM ,  Yong-Kwan Kim ,  Se-Myeong Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim

IPC: H01L21/768 ,  H01L23/522 ,  G11C11/4091 ,  H01L23/532 ,  G11C11/406 ,  G11C11/408 ,  H01L27/108 ,  H01L23/528

CPC classification number: H01L21/7682 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10885 ,  H01L28/00

Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.