公开(公告)号：US11527303B2

公开(公告)日：2022-12-13

申请号：US16890559

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

IPC: G11C29/00 ,  G06F11/20 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

公开(公告)号：US11194653B2

公开(公告)日：2021-12-07

申请号：US16668090

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Sanguhn Cha ,  Hyungi Kim ,  Hoon Shin

IPC: G06F11/10 ,  G11C29/42

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.

公开(公告)号：US12117901B2

公开(公告)日：2024-10-15

申请号：US18096053

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Sunggi Ahn ,  Jaeyoun Youn

IPC: G06F11/10

CPC classification number: G06F11/106

Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.

公开(公告)号：US20220405165A1

公开(公告)日：2022-12-22

申请号：US17535762

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Sunggi Ahn ,  Yesin Ryu ,  Sukhan Lee

IPC: G06F11/10 ,  G11C29/04

Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

公开(公告)号：US11508456B2

公开(公告)日：2022-11-22

申请号：US16685458

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Taewon Kim ,  Yoonna Oh

IPC: G11C8/00 ,  G11C29/44 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/4091 ,  G11C11/408

Abstract: A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

公开(公告)号：US11436079B2

公开(公告)日：2022-09-06

申请号：US16711557

申请日：2019-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn Cha ,  Yesin Ryu

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/15 ,  H01L25/065 ,  H01L25/16

Abstract: An error correction circuit includes an error correction code (ECC) memory and an ECC engine. The ECC memory stores an ECC, which is at least partially represented by a generation matrix. The ECC engine generates parity data based on main data using the ECC, and detects and/or corrects at least one error bit in the main data read from the memory cell array using the parity data. The main data includes a plurality of data bits divided into a plurality of sub data units. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub data units. The column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol and the mis-corrected bit is generated due to the multiple error bits in the main data.

公开(公告)号：US20210311821A1

公开(公告)日：2021-10-07

申请号：US17088900

申请日：2020-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Namsung KIM ,  Sanguhn CHA ,  Jaeyoun Youn ,  Kijun Lee

IPC: G06F11/10 ,  H01L25/065

Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.