公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20220139482A1

公开(公告)日：2022-05-05

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Hoyoun KIM ,  Suhun LIM ,  Sunghye CHO

IPC: G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

公开(公告)号：US20210311820A1

公开(公告)日：2021-10-07

申请号：US17351619

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn CHA ,  Hoyoung SONG ,  Myungkyu LEE ,  Sunghye CHO

IPC: G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US20210193245A1

公开(公告)日：2021-06-24

申请号：US16864787

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.