公开(公告)号：US20190199841A1

公开(公告)日：2019-06-27

申请号：US16229540

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Songkyu KIM ,  Yongwoon MOON ,  Insoo LEE ,  Junehee LEE ,  Sungho SEO ,  Kwangjae WOO ,  Youngil CHANG ,  Bonggoo JUN

IPC: H04M1/253 ,  H04L29/06 ,  H04M7/00

CPC classification number: H04M1/2535 ,  H04L65/1059 ,  H04L65/608 ,  H04M7/006

Abstract: An electronic device is provided. The electronic device includes a display, at least one communication circuit, and at least one processor configured to control the display and the at least one communication circuit. The at least one processor is configured to obtain a communication state using the at least one communication circuit during a packet based voice call, and to stop transmitting data associated with at least one of a plurality of background applications which operate in a background of an operating system (OS) of the electronic device when the communication state meets a specified first condition.

公开(公告)号：US20240184480A1

公开(公告)日：2024-06-06

申请号：US18438795

申请日：2024-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo NAM ,  Sungho SEO ,  Kwanwoo NOH ,  Myungsub SHIN ,  Haesung JUNG

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4278

Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

公开(公告)号：US20240085940A1

公开(公告)日：2024-03-14

申请号：US18508479

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/4291 ,  G11C7/22 ,  G11C16/32 ,  H04L7/0004 ,  H04L7/0008

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20230385209A1

公开(公告)日：2023-11-30

申请号：US18446670

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongsu KIM ,  Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

IPC: G06F13/16 ,  H04L7/00 ,  G06F1/12 ,  G06F13/40 ,  H04L1/00

CPC classification number: G06F13/1668 ,  H04L7/0008 ,  G06F1/12 ,  G06F13/4027 ,  H04L1/0002

Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.

公开(公告)号：US20230112284A1

公开(公告)日：2023-04-13

申请号：US18064002

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06 ,  G11C7/22 ,  G11C16/32 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20220113909A1

公开(公告)日：2022-04-14

申请号：US17375328

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub SHIN ,  Sungho SEO ,  Seongyong JANG ,  Haesung JUNG

IPC: G06F3/06

Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.