公开(公告)号：US12073191B2

公开(公告)日：2024-08-27

申请号：US17965351

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee

IPC: G06F7/487 ,  G06F5/01 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F7/4876 ,  G06F5/012 ,  G06F7/5443 ,  G06F9/3001

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US12182409B2

公开(公告)日：2024-12-31

申请号：US17938789

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

公开(公告)号：US12106107B2

公开(公告)日：2024-10-01

申请号：US18194174

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US11880317B2

公开(公告)日：2024-01-23

申请号：US17845441

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06 ,  G06F9/38

CPC classification number: G06F13/1668 ,  G06F3/0655 ,  G06F13/4027 ,  G06F9/3877

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

公开(公告)号：US11869571B2

公开(公告)日：2024-01-09

申请号：US17899141

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jaeyoun Youn ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C11/406 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G11C11/40618 ,  G11C7/1045 ,  G11C7/1048 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/40622

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20230402123A1

公开(公告)日：2023-12-14

申请号：US18059124

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Park ,  Sukhan Lee

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/36

CPC classification number: G11C29/46 ,  G11C29/12005 ,  G11C29/36 ,  G11C2029/3602

Abstract: Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.

公开(公告)号：US11663008B2

公开(公告)日：2023-05-30

申请号：US16814462

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US20200293319A1

公开(公告)日：2020-09-17

申请号：US16814462

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US11841763B2

公开(公告)日：2023-12-12

申请号：US17535762

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Sunggi Ahn ,  Yesin Ryu ,  Sukhan Lee

IPC: G06F11/277 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/1044 ,  G11C29/04 ,  G06F11/277

Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

公开(公告)号：US11635962B2

公开(公告)日：2023-04-25

申请号：US16814462

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.