公开(公告)号：US20210013304A1

公开(公告)日：2021-01-14

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon RYU ,  Kiyoon KANG ,  Seogoo KANG ,  Shinhwan KANG ,  Jesuk MOON ,  Byunggon PARK ,  Jaeryong SIM ,  Jinsoo LIM ,  Jisung CHEON ,  Jeehoon HAN

IPC: H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US20170287930A1

公开(公告)日：2017-10-05

申请号：US15593494

申请日：2017-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Heonkyu LEE ,  Shinhwan KANG ,  Youngwoo PARK

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

公开(公告)号：US20240243020A1

公开(公告)日：2024-07-18

申请号：US18535095

申请日：2023-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhwan KANG ,  Sunyoung Lee

IPC: H01L21/66 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L22/32 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A vertical non-volatile memory device, including a memory cell region including a plurality of gate lines overlapping each other in a vertical direction, and an insulating layer insulating the plurality of gate lines from each other in the vertical direction, an extension region on one side of the memory cell region, the extension region including a plurality of stepped connection portions having a plurality of raised pads integrally connected to each of the plurality of gate lines, a peripheral circuit structure in a lower portion of the memory cell region and the extension region, the peripheral circuit structure including a peripheral circuit wiring layer, a through type cell contact pattern in the extension region penetrating the plurality of gate lines, the insulating layer, and the plurality of stepped connection portions, and a through type cell contact monitoring pattern in the extension region spaced from the through type cell contact pattern.

公开(公告)号：US20240224521A1

公开(公告)日：2024-07-04

申请号：US18428264

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20220415909A1

公开(公告)日：2022-12-29

申请号：US17903315

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20220028731A1

公开(公告)日：2022-01-27

申请号：US17496902

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNIL SHIM ,  Shinhwan KANG ,  YOUNGHWAN SON

IPC: H01L21/762 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/761 ,  H01L27/24 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529

Abstract: Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.

公开(公告)号：US20210118902A1

公开(公告)日：2021-04-22

申请号：US16853047

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Shinhwan KANG

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02

Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

公开(公告)号：US20200343259A1

公开(公告)日：2020-10-29

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20190057898A1

公开(公告)日：2019-02-21

申请号：US15954912

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNIL SHIM ,  Shinhwan KANG ,  YOUNGHWAN SON

IPC: H01L21/762 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/761 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24

Abstract: Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.