公开(公告)号：US09858981B2

公开(公告)日：2018-01-02

申请号：US15372750

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C17/00 ,  G11C11/406 ,  G11C17/16 ,  G11C11/408 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

公开(公告)号：US09436545B2

公开(公告)日：2016-09-06

申请号：US14165820

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Sung Oh ,  Chul-Sung Park ,  Sang-Bo Lee ,  Dong-Hyun Sohn

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G11C11/00 ,  G11C29/42 ,  G11C29/44 ,  G11C11/4076 ,  G11C11/40 ,  G11C29/04 ,  G11C29/12

CPC classification number: G06F11/1048 ,  G06F11/16 ,  G11C11/005 ,  G11C11/40 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract translation: 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

公开(公告)号：US20140062864A1

公开(公告)日：2014-03-06

申请号：US14012453

申请日：2013-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Kyung LEE ,  Dong-Wook Kwon ,  Kyung-Il Kim ,  Min-Ho Kim ,  Gi-Sang Lee ,  Sang-Bo Lee ,  Young-Gu Jin ,  Jin-Wuk Choi

IPC: G06F3/01 ,  H04N13/02

CPC classification number: G06F3/017 ,  G06F3/011 ,  G06F3/0304 ,  H04N13/204

Abstract: A method and apparatus for extracting three-dimensional distance information from a recognition target is provided, which enables a gesture input from a user to be correctly recognized using distance information from the recognition target, and at the same time makes it possible to efficiently save power required for detection of the gesture input. The method includes determining if a recognition target exists within a predetermined range; when the recognition target exists within the predetermined range, generating a 3D image for the recognition target; and calculating a distance to the recognition target by using the 3D image.

Abstract translation: 提供一种用于从识别目标提取三维距离信息的方法和装置，其使得能够使用来自识别目标的距离信息来正确地识别来自用户的手势输入，并且同时可以有效地节省电力 需要检测手势输入。 该方法包括确定识别目标是否存在于预定范围内; 当识别目标存在于预定范围内时，生成用于识别目标的3D图像; 以及通过使用3D图像计算到识别目标的距离。