公开(公告)号：US20190109583A1

公开(公告)日：2019-04-11

申请号：US16212193

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Su KIM

IPC: H03K3/012 ,  H03K3/356 ,  G01R31/3185

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/356104 ,  H03K3/356139

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

公开(公告)号：US20170302279A1

公开(公告)日：2017-10-19

申请号：US15642887

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su KIM

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/356 ,  H03K3/037 ,  H03K19/20 ,  H03K3/012

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/356139 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

公开(公告)号：US20150349756A1

公开(公告)日：2015-12-03

申请号：US14824302

申请日：2015-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee KIM ,  Min-Su KIM ,  Ji-Kyum KIM ,  Emil KAGRAMANYAN ,  Dae-Seong LEE ,  Gun-Ok JUNG ,  Uk-Rae CHO

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。

公开(公告)号：US20150241519A1

公开(公告)日：2015-08-27

申请号：US14625438

申请日：2015-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung LEE ,  Min-Su KIM ,  Se-Young JANG ,  Seung-Chul CHOI

IPC: G01R31/36

CPC classification number: G01R31/382 ,  G01R31/3646 ,  G01R31/367

Abstract: A method for managing power of an electronic device and the electronic device thereof are provided. An operation method of the electronic device includes detecting a remaining battery capacity, calculating and storing a reduced ratio per unit time of the remaining battery capacity and, based on the reduced ratio, predicting a remaining operating time of the battery.

Abstract translation: 提供一种用于管理电子设备及其电子设备的电源的方法。 电子设备的操作方法包括检测剩余电池容量，计算和存储每单位时间剩余电池容量的减小比例，并且基于减小的比率来预测电池的剩余操作时间。

公开(公告)号：US20170324413A1

公开(公告)日：2017-11-09

申请号：US15661153

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su KIM

IPC: H03K19/0185 ,  H03K19/20 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356121 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

公开(公告)号：US20160365845A1

公开(公告)日：2016-12-15

申请号：US15247430

申请日：2016-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Su KIM

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/356104 ,  H03K3/356139

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

公开(公告)号：US20160124495A1

公开(公告)日：2016-05-05

申请号：US14884524

申请日：2015-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Su KIM ,  Chi-Hyun CHO ,  Seung-Chul CHOI

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3218 ,  H04W52/0264 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166 ,  Y02D70/168 ,  Y02D70/26

Abstract: An electronic device is disclosed. The electronic device may include a data provider that stores at least one piece of data for calculating a current consumption value according to each application type; and a processor that changes a data collection period according to a power state of the electronic device, collect data from the data provider, calculates the current consumption value according to each application type based on the power state of the electronic device based on the collected data, and displays the calculated current consumption value according to each application type on a display.

Abstract translation: 公开了一种电子设备。 电子设备可以包括：数据提供器，其存储用于根据每种应用类型计算当前消费值的至少一个数据; 以及处理器，其根据所述电子设备的电力状态改变数据收集期间，从所述数据提供者收集数据，基于所收集的数据，基于所述电子设备的功率状态，根据每种应用类型计算所述电流消耗值 ，并根据每种应用类型在显示器上显示计算出的电流消耗值。

公开(公告)号：US20150048876A1

公开(公告)日：2015-02-19

申请号：US14276088

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Su KIM

IPC: H03K17/284

CPC classification number: H03K17/284 ,  H03K19/0013 ,  H03K19/0016 ,  H03K2217/0054

Abstract: Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode.

Abstract translation: 提供了一种半导体电路。 半导体电路包括：输入节点，被配置为接收使能信号，感测使能信号和时钟信号; 以及时钟门控电路，被配置为当所述半导体电路处于高电平状态时，输出与所述时钟信号相对应的使能时钟信号，同时所述使能信号的信号电平处于第一电平，而与所述感测使能信号的信号电平无关; 并且当半导体电路处于低电压模式时，在使能信号和感测使能信号中的至少一个的信号电平处于第一电平的同时，输出与时钟信号相对应的使能时钟信号。