公开(公告)号：US20180158826A1

公开(公告)日：2018-06-07

申请号：US15661121

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee CHO ,  Satoru YAMADA ,  Junsoo KIM ,  Honglae PARK ,  Wonsok LEE ,  Namho JEON

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/161

CPC classification number: H01L27/10805 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/20

Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.

公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20250024665A1

公开(公告)日：2025-01-16

申请号：US18584646

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jin LEE ,  Sung Won YOO ,  Won Sok LEE ,  Min Hee CHO ,  Si Yeon CHO

IPC: H10B12/00

Abstract: The semiconductor memory device including a bit line in a first direction on a substrate, a channel structure on the bit line, and including a first vertical part in a second direction, and a second vertical part apart from the first vertical part in the first direction and in the second direction, a back-gate electrode on the bit line on a side of the channel structure and in the second direction, a back-gate insulating film between the back-gate electrode and the channel structure, a back-gate capping film on the back-gate electrode and the back-gate insulating film, a first and second word lines between the first and the second vertical parts and in the second direction, the second word line spaced apart from the first word line in the first direction and first and second capacitors connected to the first and second vertical parts, on the first and second vertical parts.

公开(公告)号：US20230157003A1

公开(公告)日：2023-05-18

申请号：US17828298

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Yongseok KIM ,  Hui-Jung KIM ,  Min Hee CHO ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/10897

Abstract: A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.

公开(公告)号：US20230084388A1

公开(公告)日：2023-03-16

申请号：US17730279

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Min Hee CHO

IPC: H01L29/786 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.

公开(公告)号：US20230055147A1

公开(公告)日：2023-02-23

申请号：US17741701

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

公开(公告)号：US20210183861A1

公开(公告)日：2021-06-17

申请号：US16930398

申请日：2020-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu LEE ,  Kiseok LEE ,  Minwoo SONG ,  Hyun-Sil OH ,  Min Hee CHO

IPC: H01L27/108 ,  G11C7/18 ,  G11C8/14

Abstract: A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

公开(公告)号：US20240282833A1

公开(公告)日：2024-08-22

申请号：US18364612

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon UHM ,  Min Hee CHO ,  Wonsok LEE ,  Wooje JUNG

IPC: H01L29/423 ,  H01L29/51 ,  H10B12/00

CPC classification number: H01L29/42364 ,  H01L29/518 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device may include a bit line on the substrate, a channel pattern on the bit line and extending in a direction perpendicular to the bit line, a word line intersecting the bit line and spaced apart from the channel pattern, a gate insulating pattern between the channel pattern and the word line, an insulating pattern on the word line, and a landing pad connected to the channel pattern. The gate insulating pattern may include a first gate insulating pattern and a second gate insulating pattern having a first dielectric constant and a second dielectric constant, respectively. The second gate insulating pattern may be between the first gate insulating pattern and the word line. The first and second dielectric constants may be different. A first width of the first gate insulating pattern may be different from a second width of the second gate insulating pattern.

公开(公告)号：US20230422511A1

公开(公告)日：2023-12-28

申请号：US18171858

申请日：2023-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeon Il LEE ,  Min Hee CHO

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40 ,  H01L23/528 ,  H01L23/522 ,  H01L29/51

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/40 ,  H01L23/5283 ,  H01L23/5226 ,  H01L29/516

Abstract: A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.

公开(公告)号：US20230389290A1

公开(公告)日：2023-11-30

申请号：US18200135

申请日：2023-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Kyunghwan LEE ,  Min Hee CHO

IPC: H10B12/00 ,  H10B53/10 ,  H10B53/30 ,  H01L29/08

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B53/10 ,  H10B53/30 ,  H01L29/0847

Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.