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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220157823A1

    公开(公告)日：2022-05-19

    申请号：US17592555

    申请日：2022-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyooho JUNG ,  Jeong-gyu SONG ,  Younsoo KIM ,  Jooho LEE

    IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02

    Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210384194A1

    公开(公告)日：2021-12-09

    申请号：US17172131

    申请日：2021-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chang-Su WOO ,  Haeryong KIM ,  Younsoo KIM ,  Sunmin MOON ,  Jeonggyu SONG ,  Kyooho JUNG

    IPC: H01L27/108

    Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

    INTEGRATED CIRCUIT DEVICE
    15.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20250081483A1

    公开(公告)日：2025-03-06

    申请号：US18636601

    申请日：2024-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeseul LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Jinwook LEE

    IPC: H10B12/00

    Abstract: An integrated circuit device includes a lower electrode, a dielectric film covering the lower electrode, an upper electrode covering the dielectric film, and a multilayered interface structure between the dielectric film and the upper electrode, wherein the multilayered interface structure includes a transition metal-aluminum (Al) complex oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al complex oxide layer being in contact with the dielectric film, and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al complex oxide layer.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250081431A1

    公开(公告)日：2025-03-06

    申请号：US18809483

    申请日：2024-08-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwook LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Yeseul LEE

    IPC: H10B12/00

    Abstract: An integrated circuit device comprising; a transistor on a substrate, and a capacitor structure electrically connected to the transistor. The capacitor structure includes a lower electrode, a lower interface film on the lower electrode, a capacitor dielectric film on the lower interface film, an upper interface film on the capacitor dielectric film, and an upper electrode on the upper interface film. The lower interface film includes a first lower interface layer including metal oxide doped with an impurity, a second lower interface layer including a material that is substantially the same as a material of the first lower interface layer and doped with nitrogen, and a third lower interface layer including a material that is identical to a material of the capacitor dielectric film and doped with nitrogen, the first to third lower interface layers being sequentially stacked on the lower electrode, and wherein the upper interface film includes a first upper interface layer including metal oxide, a second upper interface layer including a material that is identical to a material of the first upper interface layer and doped with nitrogen, and a third upper interface layer including a material that is identical to the material of the capacitor dielectric film and doped with nitrogen, the first to third upper interface layers being sequentially stacked on the upper electrode.

    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE STRUCTURE AND METHOD OF MANUFACTURING DATA STORAGE STRUCTURE
    17.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE STRUCTURE AND METHOD OF MANUFACTURING DATA STORAGE STRUCTURE 审中-公开

    公开(公告)号：US20240064999A1

    公开(公告)日：2024-02-22

    申请号：US18185586

    申请日：2023-03-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyooho JUNG

    IPC: H10B63/10 ,  H10B63/00

    CPC classification number: H10B63/10 ,  H10B63/84

    Abstract: A data storage structure may include a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer. The dielectric layer may include a metal compound having a crystalline phase and including a first metal. The dielectric layer also may include a phase control material located in an interfacial region of the dielectric layer, adjacent to the upper electrode. The phase control material may include at least one of a second metal and a metal nitride. The second metal may be configured to induce a phase change in the metal compound of the dielectric layer. The metal nitride may include the second metal.

    SEMICONDUCTOR DEVICE
    19.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230345705A1

    公开(公告)日：2023-10-26

    申请号：US18215301

    申请日：2023-06-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyooho JUNG ,  Yukyung SHIN ,  Jinho LEE

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

    Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

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