公开(公告)号：US20230255019A1

公开(公告)日：2023-08-10

申请号：US18136984

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Su WOO ,  Haeryong KIM ,  Younsoo KIM ,  Sunmin MOON ,  Jeonggyu SONG ,  Kyooho JUNG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

公开(公告)号：US20210384194A1

公开(公告)日：2021-12-09

申请号：US17172131

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Su WOO ,  Haeryong KIM ,  Younsoo KIM ,  Sunmin MOON ,  Jeonggyu SONG ,  Kyooho JUNG

IPC: H01L27/108

Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.