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公开(公告)号:US20250167861A1
公开(公告)日:2025-05-22
申请号:US19034163
申请日:2025-01-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunkee MIN , Junyoung PARK , Heetae KIM
IPC: H04B7/06
Abstract: An electronic device is disclosed. A method of operating an electronic device includes obtaining at least one of a data rate necessary for an application, a latency necessary for the application, or traffic associated with the application, communicating with an external electronic device using at least one of a plurality of antennas included in the electronic device based on the at least one of the data rate, the latency, or the traffic, and performing a control associated with a radio frequency (RF) front-end module (FEM) connected to an antenna unused for communication with the external electronic device among the plurality of antennas.
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公开(公告)号:US20230395133A1
公开(公告)日:2023-12-07
申请号:US18449066
申请日:2023-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junyoung PARK , Younghoon SON , Hyunyoon CHO , Youngdon CHOI , Junghwan CHOI
IPC: G11C11/4093 , G06F13/16 , G11C11/4076
CPC classification number: G11C11/4093 , G06F13/1668 , G11C11/4076
Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
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公开(公告)号:US20220059139A1
公开(公告)日:2022-02-24
申请号:US17323009
申请日:2021-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junyoung PARK , Jaewoo PARK , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
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公开(公告)号:US20170244890A1
公开(公告)日:2017-08-24
申请号:US15432079
申请日:2017-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wooyong LEE , Beomjoon KWON , Jaeyoel PARK , Junyoung PARK , Kihuk LEE
CPC classification number: H04N5/23216 , H04N5/2257 , H04N5/23229 , H04N5/23245 , H04N5/23293 , H04N5/772 , H04N5/907
Abstract: An electronic device may include a display, a camera module, a processor electrically coupled to the display and the camera module, and a memory electrically coupled to the processor. The memory may store instructions executed by the processor to monitor a state of the electronic device and control execution of a camera-related application based on at least one portion of a result of monitoring the state.
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公开(公告)号:US20240429189A1
公开(公告)日:2024-12-26
申请号:US18822646
申请日:2024-09-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ju-Il CHOI , Gyuho KANG , Heewon KIM , Junyoung PARK , Seong-Hoon BAE , Jin Ho AN
IPC: H01L23/00 , H01L23/532 , H01L23/538
Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.
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16.
公开(公告)号:US20240040635A1
公开(公告)日:2024-02-01
申请号:US18484812
申请日:2023-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junsu CHOI , Junyoung PARK , Hyeonu CHOI , Jeongyong MYOUNG , Junghun LEE
IPC: H04W74/08
CPC classification number: H04W74/085 , H04W74/0866
Abstract: An electronic device is provided. The electronic device includes a first processor, a communication module including a second processor, and a memory, wherein the memory includes instructions for controlling the first processor to control the communication module to perform data transmission to/reception from an access point according to a target wake time (TWT) agreement on the basis of a first TWT parameter when communicating with an access point, monitor at least one of downlink packets received from the second processor or uplink packets transferred to the second processor, estimate a TWT service period (SP) and TWT interval of a communication link level having been processed in the second processor, update the first TWT parameter with a second TWT parameter suitable for quality of service of at least one application or service operated in the first processor on the basis of the estimated TWT interval and TWT SP, and transfer the second TWT parameter to the second processor so as to make a re-agreement on TWT with the access point.
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公开(公告)号:US20240012950A1
公开(公告)日:2024-01-11
申请号:US18219955
申请日:2023-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Bogyeong KANG , Kihong KIM , Junyoung PARK , Jinsub PARK , Jaekeun OH , Youngjae JANG
CPC classification number: G06F21/79 , G06F21/602 , H04L9/0819
Abstract: Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.
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公开(公告)号:US20220166797A1
公开(公告)日:2022-05-26
申请号:US17531166
申请日:2021-11-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongryeol SHIM , Junyoung PARK
Abstract: An electronic device and a method thereof are provided. The electronic device includes a memory, and a processor configured to, based on a first signal requesting generation of a first container being input to a container management module, identify whether the first container is able to communicate using transport layer security (TLS) based on information included in the first signal through a security module, based on the identification that the first container is unable to communicate using the TLS, obtain first certificate data for communicating using the TLS based on the information included in the first signal through a certificate data management module, generate a first proxy container that is able to communicate using the TLS based on the first certificate data through the container management module, and control so that a signal inputted to access the first container is input to the first container via the first proxy container.
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公开(公告)号:US20210405683A1
公开(公告)日:2021-12-30
申请号:US17145211
申请日:2021-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junyoung PARK , YOUNG-HOON SON , HYUN-YOON CHO , YOUNGDON CHOI , JUNGHWAN CHOI
IPC: G06F1/06 , G06F13/40 , G11C11/403 , G11C11/406
Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
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公开(公告)号:US20250015009A1
公开(公告)日:2025-01-09
申请号:US18885904
申请日:2024-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ju-Il CHOI , Gyuho KANG , Un-Byoung KANG , Byeongchan KIM , Junyoung PARK , Jongho LEE , Hyunsu HWANG
IPC: H01L23/538 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/10
Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
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