公开(公告)号：US11640951B2

公开(公告)日：2023-05-02

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae Cho ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20230420403A1

公开(公告)日：2023-12-28

申请号：US18165419

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjun Song ,  Jungmin Ko ,  Taehyeong Kim ,  Youngwoo Lim ,  Dongki Choi

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L25/18 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/73 ,  H01L24/83 ,  H01L24/13 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83007 ,  H01L2224/26125 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13113 ,  H01L2224/13118

Abstract: A semiconductor package includes a base chip; semiconductor chips stacked on the base chip; bumps, a lowermost bump of the bumps disposed between the base chip and a lowermost semiconductor chip of the semiconductor chips, and each of the bumps except the lowermost bump respectively disposed between the semiconductor chips; organic material layers, a lowermost organic material layer of the organic material layers disposed between the base chip and the lowermost semiconductor chip, and each of organic material layers except the lowermost organic material layer respectively disposed between the plurality of semiconductor chips; underfill layers respectively surrounding the plurality of bumps, the underfill layers extending between the base chip and the lowermost semiconductor chip and between the semiconductor chips; and an encapsulant covering the base chip, the semiconductor chips, and the underfill layers.

公开(公告)号：US11257794B2

公开(公告)日：2022-02-22

申请号：US17030588

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun Song ,  Eunkyul Oh ,  Hyeongmun Kang ,  Jungmin Ko

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.